Abstract: A digital audio processor for a digital audio receiver having an improved automute sequence is disclosed. The digital audio processor includes automute detection circuitry that monitors the amplitude of digital audio signals before and after the application of digital filters by digital audio processing circuitry. The amplitude of the input signals are compared against a first threshold level, while the amplitude of the output signals are compared against a second threshold level. In response to the amplitude of the input signals for all of the audio channels falling below the first threshold for a selected time period, a gain stage in each channel ramps down the volume to a mute level, and pulse-width-modulation circuitry is disabled. If the output signal amplitude falls below a second threshold for a channel, the pulse-width-modulation circuitry for that channel is disabled. Hysteresis for the input signal amplitude is preferably added into the automute exit determination.

Abstract: A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal and using the clock signal for presenting an internal clock signal for use by the signal treating unit. (c) A clock simulating unit occasionally coupled with at least one of the clock signal and the clock generator provides a simulated clock signal generally similar to the internal clock signal when either of the clock signal or the internal clock signal is interrupted. (d) A control unit coupled with the signal treating unit, at least one of the clock signal input locus and the internal clock generator for selectively coupling one of the internal clock signal and the simulated clock signal for use by the signal treating unit.