Patents by Inventor Douglas B. MacGregor
Douglas B. MacGregor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5021991Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1987Date of Patent: June 4, 1991Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, John Zolnowsky, David Mothersole
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Patent number: 4994961Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1987Date of Patent: February 19, 1991Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, John Zolnowsky, David Mothersole
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Patent number: 4914578Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: January 31, 1986Date of Patent: April 3, 1990Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, David Mothersole, John Zolnowsky
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Patent number: 4887203Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.Type: GrantFiled: February 26, 1988Date of Patent: December 12, 1989Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, William C. Moyer, John E. Zolnowsky, David S. Mothersole
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Patent number: 4821231Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word, Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives whcih define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: December 21, 1987Date of Patent: April 11, 1989Assignee: Motorola, Inc.Inventors: Michael Cruess, David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4811274Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 14, 1987Date of Patent: March 7, 1989Assignee: Motorola, Inc.Inventors: Michael Cruess, David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4763253Abstract: A microcomputer has the capacity for executing instructions, requesting prefetches of instructions, and experiencing a change in instruction flow, or a branch. The microcomputer also knows in advance that a change in instruction flow is going to occur. At such time that a branch becomes known there may also be a pending instruction prefetch request. Because a branch is going to occur, there is no need to execute the prefetch. Consequently, the pending instruction prefetch is flushed which thus avoids wasting time making an unnecessary instruction prefetch.Type: GrantFiled: November 17, 1986Date of Patent: August 9, 1988Assignee: Motorola, Inc.Inventors: Mark W. Bluhm, Robert R. Thompson, David S. Mothersole, Douglas B. MacGregor
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Patent number: 4758978Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1986Date of Patent: July 19, 1988Assignee: Motorola, Inc.Inventors: Michael Cruess, David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4750110Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: April 18, 1983Date of Patent: June 7, 1988Assignee: Motorola, Inc.Inventors: David Mothersole, John Zolnowsky, Douglas B. MacGregor
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Patent number: 4745574Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.Type: GrantFiled: September 17, 1987Date of Patent: May 17, 1988Assignee: Motorola, Inc.Inventors: Robert W. Aaron, John Kuban, Douglas B. MacGregor, Robert R. Thompson
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Patent number: 4744049Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.Type: GrantFiled: September 17, 1987Date of Patent: May 10, 1988Assignee: Motorola, Inc.Inventors: John Kuban, Douglas B. MacGregor, Robert R. Thompson, David S. Mothersole
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Patent number: 4731736Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: September 18, 1986Date of Patent: March 15, 1988Assignee: Motorola, Inc.Inventors: David Mothersole, Douglas B. MacGregor, John Zolnowsky
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Patent number: 4729093Abstract: A microcomputer prioritizes data operand requests and instruction prefetch requests. Such prioritizing is established by established criteria. The established priority is altered upon the occurrence of a signal. The signal indicates a certain type of data requests. This data request type is deemed to have a higher priority than is typical for a data request. Consequently, in response to receiving the signal which indicates this data request type, the priority is altered so as to be more inclined to perform the data request. This is particularly useful when performing numerous consecutive data operations, such as a co-processor interface operation.Type: GrantFiled: March 4, 1987Date of Patent: March 1, 1988Assignee: Motorola, Inc.Inventors: David S. Mothersole, Mark W. Bluhm, Robert R. Thompson, Douglas B. MacGregor
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Patent number: 4729094Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: March 24, 1987Date of Patent: March 1, 1988Assignee: Motorola, Inc.Inventors: John Zolnowsky, David S. Mothersole, Douglas B. MacGregor, William C. Moyer
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Patent number: 4715013Abstract: A system for interfacing a processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: July 25, 1986Date of Patent: December 22, 1987Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, John Zolnowsky, David Mothersole
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Patent number: 4698747Abstract: An execution unit for a microprocessor comprising a first section for performing arithmetic and logic operations on data, a second section for performing arithmetic operations on data memory addresses, and a third section for performing arithmetic operations on instruction addresses is disclosed in which data addresses and instruction addresses may be simultaneously calculated.Type: GrantFiled: June 28, 1985Date of Patent: October 6, 1987Assignee: Motorola, Inc.Inventors: Robert R. Thompson, David S. Mothersole, Douglas B. MacGregor
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Patent number: 4649477Abstract: A data processor having size selector in a controller for explicitly selecting the size of an operand independent of an instruction in an instruction register, together with means for selectively enabling the instruction register or other functional block, or a size selector to select the size of the operand. A size bus and a size multiplexer are also provided to route the size instructions. By using this size mechanism, the amount of sequencing and control logic is significantly reduced from prior data processors. The mechanism allows operations of different sizes to be performed during a single instruction while allowing instruction dependent sizing to be done residually.Type: GrantFiled: June 27, 1985Date of Patent: March 10, 1987Assignee: Motorola, Inc.Inventors: Douglas B. MacGregor, William C. Moyer
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Patent number: 4584666Abstract: A typical feature of a data processor is a bounds check. A bounds check is achieved when a determination is made as to whether a check value, typically an address or datum, is within predetermined bounds. Such check values may be signed or unsigned. By requiring that the upper bound be numerically larger than the lower bound for doing a signed check, and requiring that the upper bound be logically larger than the lower bound for doing an unsigned check, the bounds check is performed by the data processor without the need of receiving a signal which informs the data processor in advance as to whether the check is to be signed or unsigned.Type: GrantFiled: June 21, 1984Date of Patent: April 22, 1986Assignee: Motorola, Inc.Inventors: John Zolnowsky, Edward J. Rupp, Douglas B. MacGregor
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Patent number: 4566063Abstract: A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. In response to detecting a particular sequence of a loopable instruction followed by a conditional branch instruction which selectively branches back to the loopable instruction, the data processor enters a loop mode wherein the loopable instruction and the branch instruction are internally recirculated around the pipeline to save instruction fetch cycles.Type: GrantFiled: October 17, 1983Date of Patent: January 21, 1986Assignee: Motorola, Inc.Inventors: John Zolnowsky, Douglas B. MacGregor, Kim Eckert
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Patent number: 4524415Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.Type: GrantFiled: December 7, 1982Date of Patent: June 18, 1985Assignee: Motorola, Inc.Inventors: Marvin A. Mills, Jr., William C. Moyer, Douglas B. MacGregor, John E. Zolnowsky