Abstract: Systems and techniques for network on a chip based computer architectures and distributing data without shared pointers therein are described. A described system includes computing resources; and a memory resource configured to maintain a dedicated memory region of the memory resource for distributed read operations requested by the computing resources. The computing resources can generate a packet to fetch data from the dedicated memory region without using memory addresses of respective data elements. The memory resource can receive the first packet, determine whether the first packet indicates the distributed read operation, and determine that the dedicated memory region is non-empty. Further, the memory resource can fetch one or more data elements from the dedicated memory region based on the first packet indicating the distributed read operation and the dedicated memory region being non-empty, and send a packet that includes the one or more fetched data elements.

Abstract: Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. A packet therein can specify a chain indicator to indicate inclusion in the chained packet sequence, a destination address, and an opcode. The technique includes routing the sequence to a second computing resource based on the destination address of a first chained packet in the sequence. The technique includes receiving the sequence at the second computing resource; performing the operation specified by the opcode of the first chained packet; and determining whether to process or forward one or more chained packets in a remainder portion of the sequence based on the destination address of a second chained packet of the sequence, the second chained packet being located at a beginning of the remainder portion.

Abstract: In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.

Abstract: Systems and techniques for routing and application domain security are described. A described technique includes receiving, at an internal ingress port of a router of a first chip, a first processing packet that includes a first destination identifier from a computing resource of the first chip; obtaining a first source identifier from the first chip's secured register; and routing the first processing packet to a first egress port of the router based on a determination that the first source identifier and the first destination identifier are a first authorized communication pair. The technique can include receiving, at the router's external ingress port, a transport packet, that includes a second source identifier and a second processing packet, from a second chip coupled with the first chip; and performing an authorization process based on the second source identifier and a second destination identifier before routing the second processing packet.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for application domain security. One of the methods includes maintaining, for each ingress port of a plurality of ingress ports of each top-level router of each processing device in a system, information representing one or more valid destination device ids for packets arriving at the ingress port. If an extracted destination device id of a packet received at a first ingress port of a first top-level router of a first processing device is an invalid destination device id according to information associated with the first internal ingress port, the first top-level router modifies a path of the received packet.

Abstract: Systems and techniques for network on a chip based computer architectures and distributing data without shared pointers therein are described. A described system includes computing resources; and a memory resource configured to maintain a dedicated memory region of the memory resource for distributed read operations requested by the computing resources. The computing resources can generate a packet to fetch data from the dedicated memory region without using memory addresses of respective data elements. The memory resource can receive the first packet, determine whether the first packet indicates the distributed read operation, and determine that the dedicated memory region is non-empty. Further, the memory resource can fetch one or more data elements from the dedicated memory region based on the first packet indicating the distributed read operation and the dedicated memory region being non-empty, and send a packet that includes the one or more fetched data elements.

Abstract: Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. A packet therein can specify a chain indicator to indicate inclusion in the chained packet sequence, a destination address, and an opcode. The technique includes routing the sequence to a second computing resource based on the destination address of a first chained packet in the sequence. The technique includes receiving the sequence at the second computing resource; performing the operation specified by the opcode of the first chained packet; and determining whether to process or forward one or more chained packets in a remainder portion of the sequence based on the destination address of a second chained packet of the sequence, the second chained packet being located at a beginning of the remainder portion.

Abstract: In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.

Abstract: A method for use in a computer system provides a dynamic, “self tuning” soft-error-rate-discrimination (SERD) method and apparatus. Specially designed SRAMs or other circuits are “tuned” in a manner that gives them extreme susceptibility to cosmic neutron events (soft errors), higher than that of the “regular” SRAM components, memory modules or other components in the computer system. One such specially designed SRAM is deployed per server. An interface algorithm continuously sends read/write traffic to the special SRAM to infer the soft error rate (SER), which is directly proportional to cosmic neutron flux. The inferred cosmic neutron flux rate is employed in a Poisson SPRT algorithmic approach that dynamically compensates the soft error discrimination sensitivity in accordance with the instantaneous neutron flux for all of the regular SRAM components in the server.

Abstract: A method for expressing the algorithms for the manipulation of hardware includes providing program instructions that describe a sequence of one or more transactions for manipulating hardware components of a system. The program instructions may call one or more code segments that include specific information associated with particular hardware components of the system. In addition, the program instructions are independent of the specific information. The method may also include translating the program instructions into an executable form and executing the executable form of the program instructions to manipulate the hardware components of the system from one consistent state to a next consistent state.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: The present invention is a novelty or dental device including a pair of light units secured to the inside of the mouth of a user. A flexible band is placed between the gums and lips of the user, such that the light units are placed over the molars in the back of the mouth.

Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.