Patents by Inventor Douglas Benson HUNT
Douglas Benson HUNT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11669457Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.Type: GrantFiled: August 27, 2021Date of Patent: June 6, 2023Inventors: Paul James Moyer, Douglas Benson Hunt
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Patent number: 11294710Abstract: A processing system suspends execution of a program thread based on an access latency required for a program thread to access memory. The processing system employs different memory modules having different memory technologies, located at different points in the processing system, and the like, or a combination thereof. The different memory modules therefore have different access latencies for memory transactions (e.g., memory reads and writes). When a program thread issues a memory transaction that results in an access to a memory module having a relatively long access latency (referred to as “slow” memory), the processor suspends execution of the program thread and releases processor resources used by the program thread. When the processor receives a response to the memory transaction from the memory module, the processor resumes execution of the suspended program thread.Type: GrantFiled: November 10, 2017Date of Patent: April 5, 2022Assignee: Advanced Micro Devices, Inc.Inventor: Douglas Benson Hunt
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Publication number: 20220058025Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.Type: ApplicationFiled: November 5, 2021Publication date: February 24, 2022Inventors: Paul James Moyer, Douglas Benson Hunt, Kai Troester
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Publication number: 20210390057Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventors: Paul James Moyer, Douglas Benson Hunt
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Patent number: 11169812Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.Type: GrantFiled: September 26, 2019Date of Patent: November 9, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Paul James Moyer, Douglas Benson Hunt, Kai Troester
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Patent number: 11106594Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.Type: GrantFiled: September 5, 2019Date of Patent: August 31, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Paul James Moyer, Douglas Benson Hunt
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Publication number: 20210096873Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Inventors: Paul James Moyer, Douglas Benson Hunt, Kai Troester
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Publication number: 20210073137Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.Type: ApplicationFiled: September 5, 2019Publication date: March 11, 2021Inventors: Paul James Moyer, Douglas Benson Hunt
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Patent number: 10938559Abstract: Security key identifier remapping includes associating a system-level security key identifier to a local-level identifier requiring fewer bits of storage space. The remapped security key identifiers are used to receive, at a first compute complex of a processing system, a memory access request including a memory address value and a system-level security key identifier. The compute complex responds to the memory access request based on a determination of whether a security key identifier map of the first compute complex includes a mapping of the system-level security key identifier to a local-level security key identifier. In response to determining that the security key identifier map of the first compute complex does not include a mapping of the system-level security key identifier to the local-level security key identifier, a cache miss message may be returned without probing caches of the first compute complex.Type: GrantFiled: December 12, 2017Date of Patent: March 2, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Douglas Benson Hunt
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Patent number: 10700954Abstract: A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS) floor or a current use in the control cycle by the first process exceeds the LS floor when the first setpoint exceeds the LS floor.Type: GrantFiled: December 20, 2017Date of Patent: June 30, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Douglas Benson Hunt, Jay Fleischman
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Patent number: 10613983Abstract: A method includes monitoring a request rate of speculative memory read requests from a penultimate-level cache to a main memory. The speculative memory read requests correspond to data read requests that missed in the penultimate-level cache. A hit rate of searches of a last-level cache for data requested by the data read requests is monitored. Core demand speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding core demand data read request based on the request rate and the hit rate. Prefetch speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding prefetch data read request based on the request rate and the hit rate.Type: GrantFiled: March 20, 2018Date of Patent: April 7, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Tanuj Kumar Agarwal, Anasua Bhowmik, Douglas Benson Hunt
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Patent number: 10489218Abstract: A method of monitoring, by one or more cores of a multi-core processor, speculative instructions, where the speculative instructions store data to a shared memory location, and where a semaphore, associated with the memory location, specifies the availability of the memory location to store data. One or more speculative instructions are flushed based on when the semaphore specifies the memory location is unavailable. Any further speculative instructions are suppressed from being issued based on a count of flushed speculation instructions above a specified threshold, executing the speculative instructions when the semaphore specifies the memory location is available, and storing the data to the memory location.Type: GrantFiled: December 19, 2017Date of Patent: November 26, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Douglas Benson Hunt, William E. Jones
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Publication number: 20190294546Abstract: A method includes monitoring a request rate of speculative memory read requests from a penultimate-level cache to a main memory. The speculative memory read requests correspond to data read requests that missed in the penultimate-level cache. A hit rate of searches of a last-level cache for data requested by the data read requests is monitored. Core demand speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding core demand data read request based on the request rate and the hit rate. Prefetch speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding prefetch data read request based on the request rate and the hit rate.Type: ApplicationFiled: March 20, 2018Publication date: September 26, 2019Inventors: Tanuj Kumar Agarwal, Anasua Bhowmik, Douglas Benson Hunt
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Patent number: 10366027Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.Type: GrantFiled: November 29, 2017Date of Patent: July 30, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Eric Christopher Morton, Elizabeth Cooper, William L. Walker, Douglas Benson Hunt, Richard Martin Born, Richard H. Lee, Paul C. Miranda, Philip Ng, Paul Moyer
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Publication number: 20190190805Abstract: A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS) floor or a current use in the control cycle by the first process exceeds the LS floor when the first setpoint exceeds the LS floor.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventors: Douglas Benson HUNT, Jay FLEISCHMAN
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Publication number: 20190188055Abstract: A method of monitoring, by one or more cores of a multi-core processor, speculative instructions, where the speculative instructions store data to a shared memory location, and where a semaphore, associated with the memory location, specifies the availability of the memory location to store data. One or more speculative instructions are flushed based on when the semaphore specifies the memory location is unavailable. Any further speculative instructions are suppressed from being issued based on a count of flushed speculation instructions above a specified threshold, executing the speculative instructions when the semaphore specifies the memory location is available, and storing the data to the memory location.Type: ApplicationFiled: December 19, 2017Publication date: June 20, 2019Inventors: Douglas Benson HUNT, William E. JONES
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Publication number: 20190182040Abstract: Security key identifier remapping includes associating a system-level security key identifier to a local-level identifier requiring fewer bits of storage space. The remapped security key identifiers are used to receive, at a first compute complex of a processing system, a memory access request including a memory address value and a system-level security key identifier. The compute complex responds to the memory access request based on a determination of whether a security key identifier map of the first compute complex includes a mapping of the system-level security key identifier to a local-level security key identifier. In response to determining that the security key identifier map of the first compute complex does not include a mapping of the system-level security key identifier to the local-level security key identifier, a cache miss message may be returned without probing caches of the first compute complex.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventor: Douglas Benson HUNT
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Publication number: 20190163656Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Inventors: Eric Christopher MORTON, Elizabeth COOPER, William L. WALKER, Douglas Benson HUNT, Richard Martin BORN, Richard H. Lee, Paul C. MIRANDA, Philip NG, Paul MOYER
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Publication number: 20190146831Abstract: A processing system suspends execution of a program thread based on an access latency required for a program thread to access memory. The processing system employs different memory modules having different memory technologies, located at different points in the processing system, and the like, or a combination thereof. The different memory modules therefore have different access latencies for memory transactions (e.g., memory reads and writes). When a program thread issues a memory transaction that results in an access to a memory module having a relatively long access latency (referred to as “slow” memory), the processor suspends execution of the program thread and releases processor resources used by the program thread. When the processor receives a response to the memory transaction from the memory module, the processor resumes execution of the suspended program thread.Type: ApplicationFiled: November 10, 2017Publication date: May 16, 2019Inventor: Douglas Benson HUNT