Patents by Inventor Douglas Boyle

Douglas Boyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12525001
    Abstract: Methods, systems, and computer programs are presented for the management of lane-departure (LD) events. One method includes training a classifier for LD events and loading the classifier into a vehicle. LD events are detected based on outward images using the classifier, while the turn signal is monitored to prevent false triggers. If an LD event is detected, rules are checked for alerting the driver and deciding whether to alert the driver or not. Subsequently, additional rules are checked for reporting the event and deciding whether to report the event to a Behavior Monitoring System (BMS) or to discard it. The method also includes a solid line departure model that identifies crossing dashed, solid-white, and solid-yellow lanes, delaying alerts and event generation until a significant portion of the vehicle crosses over the lane. The model also outputs a confidence score reflecting the amount of vehicle deviation from the driving lane.
    Type: Grant
    Filed: October 22, 2024
    Date of Patent: January 13, 2026
    Assignee: Samsara Inc.
    Inventors: Akshay Raj Dhamija, Abner Ayala Acevedo, Rohit Annigeri, Cole Jurden, Douglas Boyle, Jason Liu, Kevin Lai, Jose Cazarin, Pang Wu, William Nathan Hurst, Brian Westphal, Lucas Doyle, Saurabh Tripathi, Shirish Nair
  • Patent number: 12272138
    Abstract: Techniques are presented for the detection and management of collision warning (CW) events. A training dataset comprising videos of vehicle collisions and non-collisions, sensor readings, environmental conditions, and more is utilized to train a CW classification model for detecting potential collision events in vehicles. A backend CW classification model, with greater computational resources, employs a more complex neural network to review CW events received by the Behavioral Monitoring System (BMS) based on video data, achieving higher precision and reducing false positives. The CW model is installed in vehicles for real-time detection, while the backend model is deployed at the BMS. The BMS validates detected CW events, filters out false positives, and streamlines the review process for fleet administrators and customers. Additional BMS filtering operations include assessing non-proximity-related CW events and camera impairments, with the filtered CW events presented for review in the safety inbox.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: April 8, 2025
    Assignee: Samsara Inc.
    Inventors: Rohit Annigeri, Sharan Srinivasan, Kevin Lai, Jose Cazarin, Brian Westphal, Shiva Bala, Ivan Stoev, Douglas Boyle, Cole Jurden, Margaret Irene Finch, Rachel Demerly, Maya Krupa, Shirish Nair, Nathan Hurst, Yan Wang, Shaurye Aggarwal, Akshay Raj Dhamija
  • Patent number: 12165393
    Abstract: Methods, systems, and computer programs are presented for the management of lane-departure (LD) events. One method includes training a classifier for LD events and loading the classifier into a vehicle. LD events are detected based on outward images using the classifier, while the turn signal is monitored to prevent false triggers. If an LD event is detected, rules are checked for alerting the driver and deciding whether to alert the driver or not. Subsequently, additional rules are checked for reporting the event and deciding whether to report the event to a Behavior Monitoring System (BMS) or to discard it. The method also includes a solid line departure model that identifies crossing dashed, solid-white, and solid-yellow lanes, delaying alerts and event generation until a significant portion of the vehicle crosses over the lane. The model also outputs a confidence score reflecting the amount of vehicle deviation from the driving lane.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: December 10, 2024
    Assignee: Samsara Inc.
    Inventors: Akshay Raj Dhamija, Abner Ayala, Rohit Annigeri, Cole Jurden, Douglas Boyle, Jason Liu, Kevin Lai, Jose Cazarin, Pang Wu, Nathan Hurst, Brian Westphal, Lucas Doyle, Saurabh Tripathi, Shirish Nair
  • Publication number: 20050034087
    Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, availability of required features of a design in a target foundry process may be checked. The target foundry process must provide all the features that are used in the design. The design may include base wafer layers and metal stack layers. Then, a base wafer/metal stack interface layer for the design may be selected. Next, compatible blocks between different base wafer processes may be created. Then, a physical design library for the design may be created. Next, a logic design and timing library for the design may be created. This way, the design may be mapped to different foundry processes.
    Type: Application
    Filed: January 29, 2004
    Publication date: February 10, 2005
    Inventors: Christopher Hamlin, James Koford, Douglas Boyle
  • Patent number: 5517658
    Abstract: A method for testing the timing parameters of a system design is presented, especially suited for use in testing for timing violations between the pins of a semiconductor device. A description of the timing constraints of the various modules of a design is written in a common non-technical vernacular, and functions as an input file. A Timing Shell Generator converts the input file description into a simulator-environment-compatible output code-language file description. The output code-language file is operative to implement the timing constraints of the original input file during simulation such that any violations of the prescribed timing constraints are indicated to the tester who can then take appropriate action.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: May 14, 1996
    Assignee: LSI Logic Corporation
    Inventors: David Gluss, Georgia Lazana, Douglas Boyle