Abstract: One embodiment sets forth a technique for measuring chromatic dispersion using reference signals within the operational range of amplifiers used to refresh data signals. One red/blue laser pair in the transmission node is used for measuring dispersion and chromatic dispersion compensation is added at each line node in the system. Since reference and data signals propagate through each amplifier, the reference signals used to measure chromatic dispersion receive the same dispersion compensation (and will have the same residual dispersion) as the data signals. Therefore, any residual dispersion in the data signals will manifest itself in downstream dispersion measurements and, thus, can be corrected. The tunable dispersion compensator in each line node may be set to compensate for the measured dispersion, thereby compensating for both the chromatic dispersion of the link connecting the current node to the prior node and any uncorrected residual dispersion from prior nodes.

Abstract: One embodiment sets forth a technique for measuring chromatic dispersion using reference signals within the operational range of amplifiers used to refresh data signals. One red/blue laser pair in the transmission node is used for measuring dispersion and chromatic dispersion compensation is added at each line node in the system. Since reference and data signals propagate through each amplifier, the reference signals used to measure chromatic dispersion receive the same dispersion compensation (and will have the same residual dispersion) as the data signals. Therefore, any residual dispersion in the data signals will manifest itself in downstream dispersion measurements and, thus, can be corrected. The tunable dispersion compensator in each line node may be set to compensate for the measured dispersion, thereby compensating for both the chromatic dispersion of the link connecting the current node to the prior node and any uncorrected residual dispersion from prior nodes.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.

Abstract: A reduced area dynamic random access memory (DRAM) cell and method for fabricating the same wherein the cell occupies an area smaller than one photolithography pitch by two photolithography pitches through the formation of sidewall spacers along a first pattern to define a first portion of the active region of the memory cell and a second orthogonally oriented pattern to define a second portion of the active region of the memory cell thereby creating a ladder shaped active region for a column of the memory cells.

Abstract: A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.

Abstract: A temperature sensing and monitoring technique for integrated circuit devices, particularly dynamic random access memory (DRAM), which incorporates the comparison of a voltage inversely proportional to temperature to a voltage proportional to temperature thereby increasing the differential voltage vs. temperature. In a representative embodiment disclosed herein, these two voltages are designed to be equal at a given temperature and a comparison circuit produces a signal that changes from a logic level “high” to a logic level “low” at that given temperature. An additional transistor in each trip point current path forces the gate-to-source and drain-to-source voltage of current mirror transistors to be equal at the temperature trip points.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Abstract: A static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag provides a memory architecture comprising low cost DRAM memory cells that is available for system accesses 100% of the time and is capable of executing refreshes frequently enough to prevent data loss. Any subarray of the memory can be written from cache or refreshed at the same time any other subarray is read or written externally.

Abstract: A cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices, in particular cached dynamic random access memory (DRAM) and cached static random access memory (SRAM), wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby. When power-down standby is exited, the cache operations are enabled as soon as the cache, tag and control circuitry are powered-up and a clear tag sequence is executed.

Abstract: A dual-port memory substantially eliminates noise problems associated with the staggered methods of operation. The first and second word lines of a dual-port memory cell are simultaneously activated, such that all four bit lines associated with the cell also move at the same time. The dual-port memory uses simple control logic circuitry without the need for additional external control signals. There are no lock-out times or write restrictions with the method of the present invention. The dual-port memory of the present invention includes a method for hiding refresh, and a method for increasing operating speed.

Abstract: A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.

Abstract: A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.

Abstract: An integrated circuit transistor body bias regulation circuit and method of especial applicability with respect to low voltage applications wherein the threshold voltage (Vt) of certain transistors is lowered at low power supply voltage (VCC) levels, low temperature and/or high Vt process conditions to assure adequate transistor drive but may also be raised at high VCC levels, high temperature and/or low Vt process conditions to reduce leakage current. In this manner, circuit speed that is closer to constant (versus VCC, temperature and process variation) is thereby achieved.

Abstract: In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.

Abstract: In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode A remnant (60a) of a doped silicon layer overlies the S/D and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. The doped silicon acting as a dopant for the source/drain region. A nitride, preferably Si.sub.3 N.sub.4, is located under the thick dielectric and over part of the gate electrode insulation. The Si.sub.3 N.sub.4 adjoins the doped silicon to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by the doped silicon at some locations and by the nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si.sub.3 N.sub.4 but not the doped silicon.

Abstract: In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode. Titanium silicide (34) is located upon the S/D. A remnant (36a) of a (conductive) TiN layer overlies the silicide and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. A further nitride, preferably Si.sub.3 N.sub.4, is located under the thick dielectric and over part of the gate electrode insulation. The Si.sub.3 N.sub.4 adjoins the TiN to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by one nitride at some locations and by the other nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si.sub.3 N.sub.4 but not the TiN.

Abstract: Polarization retention of a ferroelectric material in a memory cell is improved by open circuiting the write pulse. The depolarizing field is reduced by allowing charge to dissipate through the ferroelectric material, causing a polarizing field.