Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of n second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth-multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two input logic gate of a second type having first and second data inputs.

Abstract: A method for simultaneously programming a plurality of antifuses each having a first electrode connected to a common node and each having a second electrode connected to an isolated node electrically isolated from the nodes of each of the other antifuses includes the steps of precharging the common node and the isolated nodes to an intermediate voltage potential selected to minimize the stress on all antifuses; precharging the isolated nodes of selected ones of the antifuses to a first programming voltage potential placing a second programming voltage potential on said common node, the first and second programming voltage potentials selected such that the difference between them is sufficient to cause programming of said antifuses and such that said intermediate potential is substantially centered between them, waiting a predetermined amount of time; and measuring the current flowing between the common node isolated nodes.

Abstract: A method for isolating a first low-voltage circuit node comprising an output of a low-voltage device from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes the step of raising the normal power supply voltage provided to the low-voltage devices to an intermediate level lower than the programming voltage but high enough to protect the outputs of the low voltage devices from damage. The output to be protected is caused to assume a desired state and is then inhibited from changing state during the programming cycle. Programming voltage is then applied to the low voltage circuit node.

Abstract: A circuit for preventing false programming of unselected anti-fuses in an anti-fuse array includes a series impedance including a plurality of transistors which may be used for partial address selection connected between a source of programming voltage and a bit line.

Abstract: A semiconductor or substrate of a first conductivity type includes a well structure of a second conductivity type formed therein. A first low voltage MOS transistor includes spaced apart source and drain regions of the first conductivity type in the well. A first transistor gate lies above a channel region which is disposed between the source and drain regions of the first low voltage MOS transistor and is separated therefrom by a gate dielectric having a first thickness. A second high voltage transistor includes spaced apart source and drain regions of the first conductivity type in the well. A second transistor gate lies above a channel region which is disposed between the source and drain regions of the second high voltage transistor and is separated therefrom by a gate dielectric having a second thickness which is greater than the thickness of the gate dielectric of the first low voltage MOS transistor.

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: The present invention includes four approaches to reduce the unintended programming of antifuses while programming selected antifuses and to decrease the programming time. The first approach includes circuitry to maintain the voltage placed on unselected antifuses at a constant level by use of a voltage source. According to the second approach, a resistor is included in series with the voltage source. According to the third approach, a diode is included in series with the voltage source. According to the fourth approach, a MOS implementation of a diode is included in series with the voltage source.

Abstract: A circuit for isolating a first low-voltage circuit mode from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes a novel two input NAND gate having one input structure configured from high voltage devices connected to the second circuit node. The other input of the NAND gate is a control input for the isolation device and is connected to a low-voltage logic signal which is high when the signal from the high programming voltage node is to be passed through to the low-voltage node and low when the low-voltage node is to be isolated from the high programming voltage node. The output of the NAND gate is connected to the first low-voltage circuit node.

Abstract: A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two-input logic gate of a second type having first and second data inputs.

Abstract: An input/output module circuit for providing input/output interface functions in integrated circuits includes an input section and an output section electrically connected to an I/O pad of the integrated circuit. The input section includes an input buffer/level shifter for translating the logic signals from the outside world to CMOS compatible levels. The input buffer may be placed in a high impedance state by a control signal applied to a control input. The output of the input buffer/level shifter is connected to a first data input of a two-input multiplexer. The output of the two-input multiplexer is connected to an internal bus and to the second data input of the two-input multiplexer. The select input of the two-input multiplexer is connected to a control signal, preferably to the same control signal used to enable the input buffer/level shifter.

Abstract: A circuit is provided for switching an internal bus of an integrated circuit between an input/output pad on the integrated circuit and a circuit node of the integrated circuit. A first switch is connected between the input/output pad and the internal bus. A second switch is connected between the circuit node and the internal bus. A high voltage detector senses the presence or absence of a voltage exceeding a preselected threshold on the input-output pad. The high voltage detector assumes a first state if the voltage on the input/output pad exceeds the preselected threshold, and assumes a second state if the voltage on the input/output pad does not exceed the preselected threshold. Switch control circuitry responsive to the high voltage detector activates either the first or second switch depending upon the output of the high voltage detector. Circuitry is provided to prevent the first and second switches from being active simultaneously and for lowering the capacitance of the input/output pad.

Abstract: A high speed static single ended sense amplifier is disclosed, including, an input node, an output node, a first P-channel input transistor having its source connected to a source of positive voltage, its drain connected to the input node and its gate connected to a feedback node, a first N-channel input transistor having its drain connected to the input node, its source connected to a source of negative voltage and its gate connected to the feedback node, a first output P-channel transistor having its source connected to a source of positive voltage, its drain connected to the output node, and its gate connected to the feedback node, a first N-channel output transistor having its drain connected to the output node, its source connected to a source of positive voltage and its gate connected to the feedback node, an N-channel feedback transistor having its gate connected to the output node, its drain connected to a source of positive voltage and its source connected to the feedback node, a capacitive voltage d

Abstract: The high-speed static differential sense amplifier of the present invention is composed of two stages. The first stage uses a source follower to feed a set of dual complimentary current mirrors. The current mirrors in the source of the input devices convert the voltage difference supplied by the source follower into a current. This current is mirrored into the second stage by opposing pull-down and pull-up current mirrors from the first stage. The second stage current difference produces the large voltage swings needed to drive the digital logic.

Abstract: The high-speed static differential sense amplifier of the present invention is composed of two stages. The first stage uses a source follower to feed a set of dual complimentary current mirrors. The current mirrors in the source of the input devices convert the voltage difference supplied by the source follower into a current. This current is mirrored into the second stage by opposing pull-down and pull-up current mirrors from the first stage. The second stage current difference produces the large voltage swings needed to drive the digital logic.

Abstract: A sense amplifier for use in a CMOS static random access memory. The core of the sense amplifier comprises seven transistors: two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from the pull down node during sensing operations, and a four transistor latch coupled to the drains of the two sensing transistors. The four transistor latch comprises two cross coupled CMOS inverters. When the pull down transistor is activated, the four transistor latch automatically amplifies the voltage differential on the gates of the two sensing transistors, typically latching in less than two nanoseconds. Since the latch is made up of CMOS inverters, no d.c. current is drawn by the sense amplifier after the input data has been sensed and latched. As a result, relatively powerful transistors can be used in the sense amplifier.

Abstract: The present invention utilizes a pair of coils, one beneath the skin and one outside the skin, each connected to a capacitor. The values of the capacitor and coil inductance are selected to provide a stagger-tuned link. That is, the values of the components are selected to place the pole of one filter above the operating frequency, and the pole of the other filter below the operating frequency of the link. The poles will move as the coupling coefficient changes, desensitizing the link to the coupling so that the coils can be misaligned in any manner with little effect on the output.A fully active driver or class D amplifier is preferably utilized to effectively drive the link with a square wave signal. This signal can be modulated to convey data information to the implanted receiver coil beneath the skin.

Abstract: A combination of a transmitter and implantable receiver are disclosed wherein data is conveyed from transmitter to receiver utilizing a data format in which each channel to be stimulated is adapted to convey information in monopolar, bipolar or analog form.The data format includes two types of code words: transition words in which one bit is assigned to each channel and can be used to create monopolar pulsatile or bipolar pulsatile waveforms; and amplitude words which can create analog waveforms one channel at a time.An essential element of the output system is a current source digital to analog converter which responds to the code words to form the appropriate output on each channel. Each output is composed of a set of eight current sources, four with one polarity of current and the other four with the opposite polarity of current. In each group of four, the current sources are binarily related, I, 2I, 4I and 8I.