Abstract: A compound of Formula I, is provided. In Formula I, one of Z1, Z2, and Z3 is N and the remainder are C; each of L1 and L2 is independently selected from a direct bond and a linking group; at least one of R1, R2, RA, RB, RC, RD, and RE comprises a group R* having a structure selected form the group consisting of Formula II, -Q(R3)(R4)a(R5)b, Formula III, and Formula IV, Each R, R?, R?, R1, R2, R3, R4, R5, RA, RB, RC, RD, RE, RF, RG, and RH is independently hydrogen or a General Substituent, with the proviso that group R* is not adamantyl. Formulations, OLEDs, and consumer products containing the compound are also provided.

Abstract: Nucleic acid molecules derived from sequences of novel human parvovirus B19 variant genomes are provided. Also provided are assays and kits comprising the nucleic acid molecules.

Abstract: In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.

Abstract: In an embodiment, a peripheral component may include multiple sources of commands, such as command queues and/or macro memories. The commands may be performed in the peripheral component and may result in an error. The peripheral component may include a trace queue into which the commands may be written, independent of the source of the commands. Thus, the trace queue may provide a record of recently performed commands.

Abstract: Nucleic acid molecules derived from sequences of novel human parvovirus B19 variant genomes are provided. Also provided are assays and kits comprising the nucleic acid molecules.

Abstract: A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.

Abstract: A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.

Abstract: A method and apparatus for training a DLL in a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory coupled to convey data read therefrom on one or more channels. Each memory channel may include a delay locked loop (DLL) configured to apply a desired amount of delay to a data strobe signal received from the memory during a read operation. Upon detecting a read request, a controller may initiate a training procedure in which the DLL is trained to the desired delay. During the training procedure, an input clock signal may be provided to the DLL. The delay within the DLL may be adjusted until an output clock signal has a desired phase relationship with the input clock signal. Once the desired phase relationship is attained, the training procedure may be terminated and the DLL input may be switched to receive the data strobe signal.

Abstract: In an embodiment, a peripheral component may include multiple sources of commands, such as command queues and/or macro memories. The commands may be performed in the peripheral component and may result in an error. The peripheral component may include a trace queue into which the commands may be written, independent of the source of the commands. Thus, the trace queue may provide a record of recently performed commands.

Abstract: A method and apparatus for training a DLL in a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory coupled to convey data read therefrom on one or more channels. Each memory channel may include a delay locked loop (DLL) configured to apply a desired amount of delay to a data strobe signal received from the memory during a read operation. Upon detecting a read request, a controller may initiate a training procedure in which the DLL is trained to the desired delay. During the training procedure, an input clock signal may be provided to the DLL. The delay within the DLL may be adjusted until an output clock signal has a desired phase relationship with the input clock signal. Once the desired phase relationship is attained, the training procedure may be terminated and the DLL input may be switched to receive the data strobe signal.

Abstract: In an embodiment, a peripheral component may include a command queue configured to store a set of commands to perform a transfer on a peripheral interface. Some of the commands may be long-latency commands, and the long-latency commands may be aborted to perform higher priority commands. In an embodiment, each command may have an abort attribute assigned by software which indicates whether or not the command is abortable. If a higher priority command needs to be performed while the long-latency command is in progress, the command may be aborted. In an embodiment, software may write an abort field in a control register to cause the long-latency command to be aborted.

Abstract: In an embodiment, a data scramble/descramble circuit for a memory may employ multiple scramble circuits that may provide randomization of data across both rows and columns of a memory array. The first circuit may receive at least a portion of the address of the row, and may produce an output value by logically operating on the portion of the address. The second circuit may receive the output of the first circuit (or a portion thereof) as a seed, and may scramble the data to be written to memory. In one embodiment, a least significant portion of the address may be operated upon by the first circuit (e.g. the least significant byte), which may be most likely to change from row to row as compared to other portions of the address.

Abstract: In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Abstract: In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.

Abstract: In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Abstract: In an embodiment, a data scramble/descramble circuit for a memory may employ multiple scramble circuits that may provide randomization of data across both rows and columns of a memory array. The first circuit may receive at least a portion of the address of the row, and may produce an output value by logically operating on the portion of the address. The second circuit may receive the output of the first circuit (or a portion thereof) as a seed, and may scramble the data to be written to memory. In one embodiment, a least significant portion of the address may be operated upon by the first circuit (e.g. the least significant byte), which may be most likely to change from row to row as compared to other portions of the address.

Abstract: In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Abstract: In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.

Abstract: An improved process for the purification of antibodies from human plasma or other sources is disclosed. The process involves suspension of the antibodies at pH 3.8 to 4.5 followed by addition of caprylic acid and a pH shift to pH 5.0 to 5.2. A precipitate of contaminating proteins, lipids and caprylate forms and is removed, while the majority of the antibodies remain in solution. Sodium caprylate is again added to a final concentration of not less than about 15 mM. This solution is incubated for 1 hour at 25° C. to affect viral inactivation. A precipitate (mainly caprylate) is removed and the clear solution is diluted with purified water to reduce ionic strength. Anion exchange chromatography using two different resins is utilized to obtain an exceptionally pure IgG with subclass distribution similar to the starting distribution. The method maximizes yield and produces a gamma globulin with greater than 99% purity. The resin columns used to obtain a high yield of IgG retain IgM and IgA.

Abstract: An improved process for the purification of antibodies from human plasma or other sources is disclosed. The process involves suspension of the antibodies at pH 3.8 to 4.5 followed by addition of caprylic acid and a pH shift to pH 5.0 to 5.2. A precipitate of contaminating proteins, lipids and caprylate forms and is removed, while the majority of the antibodies remain in solution. Sodium caprylate is again added to a final concentration of not less than about 15 mM. This solution is incubated for 1 hour at 25° C. to effect viral inactivation. A precipitate (mainly caprylate) is removed and the clear solution is diluted with purified water to reduce ionic strength. Anion exchange chromatography using two different resins is utilized to obtain an exceptionally pure IgG with subclass distribution similar to the starting distribution. The method maximizes yield and produces a gamma globulin with greater than 99% purity. The resin columns used to obtain a high yield of IgG retain IgM and IgA.