Abstract: Methods and systems may involve determining a user attention level based on video stream data associated with a first participant in an always-on video conferencing session. The video stream data may be modified based on the user attention level to obtain modified video stream data that is automatically adjusted for privacy. In addition, the modified video stream data may be transmitted to one or more other participants in the video conferencing session.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: Methods and systems may involve determining a user attention level based on video stream data associated with a first participant in an always-on video conferencing session. The video stream data may be modified based on the user attention level to obtain modified video stream data that is automatically adjusted for privacy. In addition, the modified video stream data may be transmitted to one or more other participants in the video conferencing session.

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Abstract: Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

Abstract: Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.

Abstract: A hierarchical power control system for an integrated circuit may be integrated into a clocking system that includes a global clock generator, a clock distribution network in communication with the global clock generator and a plurality of functional unit blocks each in communication with the global clock generator. The hierarchical power control system may include a first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block.

Abstract: A micro processor including a bus fraction register with an encoding which when decoded indicates either a bus fraction encoding or a stop clock function, data processing logic that includes a number of units including a bus unit, arranged as an instruction pipeline. The units are clocked by an internal clock running at a first frequency and operating with an I/O bus clocked by an I/O clock running at a second frequency which is a fraction of the first frequency. A stop clock signal is generated upon the condition that the bus fraction register contains the stop clock encoding. A bus unit busy (BBSY) signal line is polled to ensure that all pending bus cycles in the pipeline are completed, the polling being initiated in response to the stop clock signal. A special cycle encoded to indicate the stop clock function is run to inform the units of the microprocessor that the internal and I/O clocks are going to stop toggling.

Abstract: A method and apparatus for sizing components of an electronic circuit by replacing standard cells representative of the components in the circuit with other standard cells from a standard cell library in order to improve the performance so that the circuit meets certain predetermined user-specified criteria. A computer program implementation ("the sizing system") of this method is described. This implementation receives command line options from the user, builds an internal representation of the external standard cell library, builds a database describing the connectivity of the circuit, computes the capacitance seen at each node in the circuit, and queries the user for additional command options. One such option is for the sizing system to size the circuit, via a heuristic algorithm, by replacing standard cells in the circuit with others from a standard cell library in order to improve the circuit's performance.