Patents by Inventor Douglas Cassel
Douglas Cassel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862215Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.Type: GrantFiled: August 27, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Sateesh Talasila, Chandrasekhar Mandalapu, Robert Douglas Cassel, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Srivatsan Venkatesan
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Patent number: 11715520Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells.Type: GrantFiled: April 5, 2021Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Robert Douglas Cassel, Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango
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Publication number: 20230069190Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Sateesh Talasila, Chandrasekhar Mandalapu, Robert Douglas Cassel, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Srivatsan Venkatesan
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Publication number: 20230018390Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: ApplicationFiled: September 13, 2022Publication date: January 19, 2023Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Patent number: 11514985Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: GrantFiled: April 5, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319595Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells.Type: ApplicationFiled: April 5, 2021Publication date: October 6, 2022Inventors: Robert Douglas Cassel, Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango
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Publication number: 20220319594Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.Type: ApplicationFiled: May 25, 2022Publication date: October 6, 2022Inventors: Srivatsan Venkatesan, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20220319592Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.Type: ApplicationFiled: April 5, 2021Publication date: October 6, 2022Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Patent number: 11348640Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion.Type: GrantFiled: April 5, 2021Date of Patent: May 31, 2022Assignee: Micron Technology, Inc.Inventors: Srivatsan Venkatesan, Sundaravadivel Rajarajan, Iniyan Soundappa Elango, Robert Douglas Cassel
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Publication number: 20050255150Abstract: Methods and topical patches for outpatient treatment of moderate to severe pain with an opioid, for example, the pain caused by surgically closed wounds. The methods and patches of the invention comprise: (1) a local-anesthetic component for local delivery of a local anesthetic; and (2) an opioid component for transdermal delivery of an opioid. The synergistic combination of a local anesthetic and an opioid provides effective relief of moderate to severe pain at lower opioid doses than current opioid treatments.Type: ApplicationFiled: April 25, 2005Publication date: November 17, 2005Inventors: Douglas Cassel, Kirti Valia
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Publication number: 20040058994Abstract: A non-invasive and non-systemic method for intradermal prevention OR amelioration of pain from a surgically closed wound is disclosed. The method comprises topical delivery of a local anesthetic to an exterior surface of a surgically closed wound.Type: ApplicationFiled: September 25, 2003Publication date: March 25, 2004Applicant: EpiCept CorporationInventor: R. Douglas Cassel
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Patent number: 6645521Abstract: A non-invasive and non-systemic method for intradermal prevention OR amelioration of pain from a surgically closed wound is disclosed. The method comprises topical delivery of a local anesthetic to an exterior surface of a surgically closed wound.Type: GrantFiled: May 3, 2002Date of Patent: November 11, 2003Assignee: EpiCept CorporationInventor: R. Douglas Cassel
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Publication number: 20020128285Abstract: A non-invasive and non-systemic method for intradermal prevention OR amelioration of pain from a surgically closed wound is disclosed. The method comprises topical delivery of a local anesthetic to an exterior surface of a surgically closed wound.Type: ApplicationFiled: May 3, 2002Publication date: September 12, 2002Applicant: American Pharmed Labs, Inc.Inventor: R. Douglas Cassel
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Patent number: 6383511Abstract: A non-invasive and non-systemic method for intradermal prevention OR amelioration of pain from a surgically closed wound is disclosed. The method comprises topical delivery of a local anesthetic to an exterior surface of a surgically closed wound.Type: GrantFiled: October 25, 1999Date of Patent: May 7, 2002Assignee: EpiCept CorporationInventor: R. Douglas Cassel
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Patent number: 5911252Abstract: A system and method for automated filling of one or more medical syringes with desired volume(s) and concentration(s) of an injectate solution, such as a contrast solution usable for medical imaging procedures (e.g., x-ray, MRI, ultrasound). The system may incorporate an automated syringe magazine which interfaces with the programmable system controller to deliver the desired number of syringes after the syringes have been filled. Also, the system may utilize a low-pressure pumping arrangement wherein a pumping device engages each receiving syringe and withdraws the plunger of the receiving syringe to pull the desired injectate solution into the receiving syringe by negative pressure.Type: GrantFiled: April 29, 1997Date of Patent: June 15, 1999Inventor: Douglas Cassel
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Patent number: 5823363Abstract: An article of manufacture which is constructed to receive and hold a plurality of syringes of differing size. The article comprises a substantially rigid frame having a plurality of syringe-receiving cavities formed therein. Each of the syringe-receiving cavities is sized and configured to receive and hold a syringe in a generally vertical orientation. At least some of the syringe-receiving cavities comprise variable diameter syringe-receiving cavities which are adapted to receive different sizes of syringes.Type: GrantFiled: October 18, 1996Date of Patent: October 20, 1998Inventor: Douglas Cassel