Abstract: Aspects for increasing yield in an embedded memory device are described. With the aspects of the present invention, a cache is provided for a memory unit of an embedded memory device. Attempts to access a failed bit memory location in the memory unit are determined. When a failed memory bit location is being accessed, substitution of a memory location in the cache for the failed bit memory location occurs.

Abstract: Aspects for generating CRT timing signals in a graphics accelerator are described. A method aspect includes shifting reference count values forward by a predetermined count period. A single comparator is utilized to perform a plurality of comparisons between CRT timing signals and at least one of the reference count values during the predetermined count period. Further, compensation for the shifting forward occurs by shifting back signals output from the single comparator. With the present invention, CRT timing signals are generated through time-shifting of relevant signals. The time-shifting further allows the utilization of a single comparator, which reduces the logic gate requirement and thus the area and cost.