Abstract: A pattern inspection apparatus and method that uses multiple images in a pattern recognition process used to detect defects in an object being inspected is disclosed. A user is provided with multiple image selection windows allowing the user to select multiple desired images from the object to form a pattern to be recognized within the object. The multiple desired images will be substantially free from undesired features of the object. Once the multiple desired images are selected, the spatial relationship between them is determined and used to learn the pattern to be recognized. The spatial relationship between the desired images further filters out undesired features. The pattern to be recognized is used in a subsequent pattern recognition analysis. Since the pattern to be recognized includes only desired images and their relationship, undesired features that could corrupt the pattern recognition analysis are not present during the analysis.

Abstract: The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.

Abstract: The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.