Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

Abstract: In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed.

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.