Abstract: In order to reduce the traffic over the communication bus between the host processing unit and an emulator server unit during the test of a target processing unit, the commands are divided into groups of test commands. A group of commands is transferred to the emulator server unit and stored in a memory unit of the emulator server unit. The emulator server unit then applies each command of the group of commands to a target processing unit. The resultant data generated as a result of the application of each command is stored in the emulator server unit. When all the commands of the group of commands have been executed by the target processing unit and the resultant data stored in the emulator server unit, the resultant data is transferred to the host processing unit in a single communication bus access.

Abstract: A reconfigurable cable/pod unit replaces the cable/pod unit coupling an emulation unit and a target processor. The reconfigurable cable/pod unit includes the discrete logic elements, a programmable unit and interface logic. The programmable unit and the interface unit permit the pod unit to assign conductors to the coupled cable. The interface unit includes storage and other logic elements that compensate for the differences in clock speeds and in rates of data exchange between the emulation unit and the target processor. No changes are necessary in the emulation unit to use the reconfigurable cable/pod unit. The reconfigurable cable pod unit permits, by changing the programming in the programmable unit, to operate in selectable modes, to provide a selectable interface to the target processor, to implement changes and upgrades in the testing procedures, and to test different types of target processors.

Abstract: An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.

Abstract: A reconfigurable cable/pod unit is adapted to replace the cable/pod unit coupling an emulation unit and a target processor. The original cable/pod unit includes discrete logic elements in the pod unit that provides an interface for exchanging JTAG and related timing and control signals between the emulation unit and the target processor. The reconfigurable cable/pod unit includes the discrete logic elements, a programmable unit and interface logic. The programmable unit and the interface unit permit the pod unit to assign the conductors of the coupled cable. The interface unit includes storage and other logic elements that compensate for differences in clock speeds and in rates of data exchange between the emulation unit and the target processor. No changes are necessary in the emulation unit to use the reconfigurable cable/pod unit.

Abstract: A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor.

Abstract: In order to reduce the traffic over the communication bus between the host processing unit and an emulator server unit during the test of a target processing unit, the commands are divided into groups of test commands. A group of commands is transferred to the emulator server unit and stored in a memory unit of the emulator server unit. The emulator server unit then applies each command of the group of commands to a target processing unit. The resultant data generated as a result of the application of each command is stored in the emulator server unit. When all the commands of the group of commands have been executed by the target processing unit and the resultant data stored in the emulator server unit, the resultant data is transferred to the host processing unit in a single communication bus access.

Abstract: An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Microprocessor 1 is operable to halt in response to an emulation event with partially completed instructions still in the execution pipeline.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. During emulation, the fetching of instructions from program memory can be halted.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: The invention provides a method for interrupting processing by a processor. The method includes the step of requesting an analysis interrupt by setting a bit in a register in the processor (119), the bit associated with an analysis interrupt, the analysis interrupt having a configurable priority. The method also includes the step of detecting the analysis interrupt request. The method further comprises assigning an assigned priority level (114) to the analysis interrupt from a range of priority levels and processing the analysis interrupt (124) based on the assigned priority level.The invention also provides a processor having a memory unit (14, 16) and a central processing unit (12) operable to access the memory unit. The central processing unit (12) includes an interrupt priority parameter storage system (80) for storing an interrupt priority parameter.