Abstract: A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.