Patents by Inventor Douglas E. Jewett

Douglas E. Jewett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8271606
    Abstract: A network-based storage system comprises one or more block-level storage servers that connect to, and provide disk storage for, one or more host computers. In one embodiment, the system is capable of subdividing the storage space of an array of disk drives into multiple storage partitions, and allocating the partitions to host computers on a network. A storage partition allocated to a particular host computer may appear as local disk drive storage to user-level processes running on the host computer.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: September 18, 2012
    Assignee: Summit Data Systems LLC
    Inventors: Douglas E. Jewett, Adam J. Radford, Bradley D. Strand, Jeffrey D. Chung, Joel D. Jacobson, Robert B. Haigler, Rod S. Thompson, Thomas L. Couch
  • Publication number: 20080313301
    Abstract: A network-based storage system comprises one or more block-level storage servers that connect to, and provide disk storage for, one or more host computers. In one embodiment, the system is capable of subdividing the storage space of an array of disk drives into multiple storage partitions, and allocating the partitions to host computers on a network. A storage partition allocated to a particular host computer may appear as local disk drive storage to user-level processes running on the host computer.
    Type: Application
    Filed: August 20, 2008
    Publication date: December 18, 2008
    Inventors: Douglas E. Jewett, Adam J. Radford, Bradley D. Strand, Jeffrey D. Chung, Joel D. Jacobson, Robert B. Haigler, Rod S. Thompson, Thomas L. Couch
  • Publication number: 20080313187
    Abstract: A network-based storage system comprises one or more block-level storage servers that connect to, and provide storage for, one or more host computers over logical network connections, such as TCP/IP connections. In one embodiment, the block-level storage servers implement a protocol through which a storage server authenticates a host before permitting the host to access storage resources. Upon successful authentication, the storage server may also provide access information to the host.
    Type: Application
    Filed: August 20, 2008
    Publication date: December 18, 2008
    Inventors: Douglas E. Jewett, Adam J. Radford, Bradley D. Strand, Jeffrey D. Chung, Joel D. Jacobson, Robert B. Haigler, Rod S. Thompson, Thomas L. Couch
  • Patent number: 7428581
    Abstract: A network-based storage system comprises one or more block-level storage servers that connect to, and provide disk storage for, one or more host computers (“hosts”) over logical network connections (preferably TCP/IP sockets). In one embodiment, each host can maintain one or more socket connections to each storage server, over which multiple I/O operations may be performed concurrently in a non-blocking manner. The physical storage of a storage server may optionally be divided into multiple partitions, each of which may be independently assigned to a particular host or to a group of hosts. When a host initially connects to a storage server in one embodiment, the storage server initially authenticates the host, and then notifies the host of the ports that may be used to establish data connections and of the partitions assigned to that host.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: September 23, 2008
    Assignee: Applied Micro Circuits Corporation
    Inventors: Douglas E. Jewett, Adam J. Radford, Bradley D. Strand, Jeffrey D. Chung, Joel D. Jacobson, Robert B. Haigler, Rod S. Thompson, Thomas L. Couch
  • Patent number: 7392291
    Abstract: A network-based storage system comprises one or more block-level storage servers that connect to, and provide disk storage for, one or more host computers (“hosts”) over logical network connections (preferably TCP/IP sockets). In one embodiment, each host can maintain one or more socket connections to each storage server, over which multiple I/O operations may be performed concurrently in a non-blocking manner. The physical storage of a storage server may optionally be divided into multiple partitions, each of which may be independently assigned to a particular host or to a group of hosts. Host driver software presents these partitions to user-level processes as one or more local disk drives. When a host initially connects to a storage server in one embodiment, the storage server initially authenticates the host, and then notifies the host of the ports that may be used to establish data connections and of the partitions assigned to that host.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: June 24, 2008
    Assignee: Applied Micro Circuits Corporation
    Inventors: Douglas E. Jewett, Adam J. Radford, Bradley D. Strand, Jeffrey D. Chung, Joel D. Jacobson, Robert B. Haigler, Rod S. Thompson, Thomas L. Couch
  • Publication number: 20020138704
    Abstract: A method and apparatus for providing paired or shadowed shared memory within UNIX and UNIX-like environments is provided. For the present invention shared memory segments, established using System V-like shared memory commands, are registered or paired. Once paired checkpointing operations may be performed by pushing or pulling data between paired segments. These checkpointing operations may be synchronous or asynchronous. The present invention also allows client processes to determine the status of shared memory segments and the status of checkpointing requests.
    Type: Application
    Filed: December 15, 1998
    Publication date: September 26, 2002
    Inventors: STEPHEN W. HISER, STEPHEN H. MILLER, JAMES R. ALEXANDER, THOMAS J. DAVIDSON, DOUGLAS E. JEWETT, GLEN W. GORDON, DAVID P. SONNIER
  • Publication number: 20020049825
    Abstract: A network-based storage system comprises one or more block-level storage servers that connect to, and provide disk storage for, one or more host computers (“hosts”) over logical network connections (preferably TCP/IP sockets). In one embodiment, each host can maintain one or more socket connections to each storage server, over which multiple I/O operations may be performed concurrently in a non-blocking manner. The physical storage of a storage server may optionally be divided into multiple partitions, each of which may be independently assigned to a particular host or to a group of hosts. Host driver software presents these partitions to user-level processes as one or more local disk drives. When a host initially connects to a storage server in one embodiment, the storage server initially authenticates the host, and then notifies the host of the ports that may be used to establish data connections and of the partitions assigned to that host.
    Type: Application
    Filed: August 10, 2001
    Publication date: April 25, 2002
    Inventors: Douglas E. Jewett, Adam J. Radford, Bradley D. Strand, Jeffrey D. Chung, Joel D. Jacobson, Robert B. Haigler, Rod S. Thompson, Thomas L. Couch
  • Patent number: 6263452
    Abstract: A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: July 17, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, Krayn W. Fey, Jr., John Posdro, Kenneth C. Debacker, Nikhil A. Mehta
  • Patent number: 6073251
    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: June 6, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Krayn W. Fey, Jr., John Posdro, Kenneth C. DeBacker, Nikhil A. Mehta
  • Patent number: 5890003
    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
    Type: Grant
    Filed: September 7, 1993
    Date of Patent: March 30, 1999
    Assignee: Tandem Computers Incorporated
    Inventors: Richard W. Cutts, Jr., Kenneth C. Debacker, Robert W. Horst, Nikhil A. Mehta, Douglas E. Jewett, John David Allison, Richard A. Southworth
  • Patent number: 5588111
    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: December 24, 1996
    Assignee: Tandem Computers, Incorporated
    Inventors: Richard W. Cutts, Jr., Randall G. Banton, Douglas E. Jewett
  • Patent number: 5388242
    Abstract: A computer system employs multiple CPUs, all executing the same instruction stream, with multiple, identical memory modules storing duplicates of the same data and accessable by all the CPUs, providing global memory. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously. Each CPU has its own fast cache and also a local memory not accessable by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernal is kept in local memory. This arrangement is particularly useful in fault-tolerant computer systems.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: February 7, 1995
    Assignee: Tandem Computers Incorporated
    Inventor: Douglas E. Jewett
  • Patent number: 5327553
    Abstract: A fault-tolerant computer system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical directory in this filesystem contains a file for each component; each file maps to either a hardware component or a software module. The pseudo-filesystem hierarchy is determined during system initialization and is automatically updated whenever the software or hardware configuration changes. The pseudo-filesystem, called /config filesystem herein, is implemented as a Unix filesystem in the Unix filesystem switch. This pseudo-filesystem method may be implemented in a fault-tolerant, redundant computer system configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: July 5, 1994
    Assignee: Tandem Computers Incorporated
    Inventors: Douglas E. Jewett, Tom Bereiter, Brian Vetter
  • Patent number: 5317752
    Abstract: A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. This powerfail/autorestart procedure may be implemented in a fault-tolerant multiprocessor configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: May 31, 1994
    Assignee: Tandem Computers Incorporated
    Inventors: Douglas E. Jewett, Phil Webster, Dave Aldridge, Peter C. Norwood, Nikhil A. Mehta
  • Patent number: 5295258
    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.
    Type: Grant
    Filed: January 5, 1990
    Date of Patent: March 15, 1994
    Assignee: Tandem Computers Incorporated
    Inventors: Douglas E. Jewett, Tom Bereiter, Brian Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Kyran W. Fey, Jr., John Pozdro, Kenneth C. Debacker, Nikhil A. Mehta
  • Patent number: 5276823
    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.
    Type: Grant
    Filed: March 5, 1991
    Date of Patent: January 4, 1994
    Assignee: Tandem Computers Incorporated
    Inventors: Richard W. Cutts, Jr., Randall G. Banton, Douglas E. Jewett
  • Patent number: 5193175
    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
    Type: Grant
    Filed: March 6, 1991
    Date of Patent: March 9, 1993
    Assignee: Tandem Computers Incorporated
    Inventors: Richard W. Cutts, Jr., Peter C. Norwood, Kenneth C. DeBacker, Nikhil A. Mehta, Douglas E. Jewett, John D. Allison, Robert W. Horst
  • Patent number: 4965717
    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.
    Type: Grant
    Filed: December 13, 1988
    Date of Patent: October 23, 1990
    Assignee: Tandem Computers Incorporated
    Inventors: Richard W. Cutts, Jr., Nikhil A. Mehta, Douglas E. Jewett