Abstract: A memory system for providing a contiguous address space and including several memory modules each having circuitry to provide information of their respective memory module capacity to a control circuit. The control circuit allocates a start address to the first memory module and allocates start addresses to the remaining memory modules in accordance with previously allocated start addresses and the memory capacities of the memories that have received their respected start addresses. In one embodiment, the control circuit includes a series of adders each connected to a memory module to receive memory capacity data. The adders are connected in series to compute the start addresses in a daisy chain fashion.

Abstract: A circuit for terminating the scanning operation of a signal seeking receiver includes a double-ended limit detector which responds to the AFC voltage developed in the receiver to produce a stop signal when the frequency deviations of the IF signal are within a narrow band centered about 10.7 Mhz.