Abstract: A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line.

Abstract: A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/0) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line.

Abstract: A system and method are provided to avoid deadlocks when performing non-atomic operations on data in a shared memory accessed by multiple processors, whereby the shared memory sends messages to implement a split lock. Via the messages, the requesting processor is granted exclusive access to the shared memory so that no other processor may access the same data until after the non-atomic operation has completed. The messages used to avoid the deadlock include a split lock request, a lock message, a grant message, a gone idle message and a release idle message. By using the above messages, the system accepts requests from multiple processors for exclusive access to memory, orders all of the requests, and awards exclusive access to the first processor to make a request. The system can include a cache memory, associated with a requesting processor, which sends a lock request to the main memory in response to a split lock request from a requesting processor.

Abstract: A computer system comprises a plurality of processing modules that can be configured into different partitions within the computer system, and a main memory. Each partition operates under the control of a separate operating system. At least one shared memory window is defined within the main memory to which multiple partitions have shared access, and each partition may also be assigned an exclusive memory window. Program code executing on different partitions enables those partitions to communicate with each other through the shared memory window. Means are also provided for mapping the physical address space of the processors in each partition to the respective exclusive memory windows assigned to each partition, so that the exclusive memory windows assigned to each partition appear to the respective operating systems executing on those partitions as if they all start at the same base address.

Abstract: A system and method for avoiding deadlocks when performing non-atomic operations on data in a shared memory accessed by multiple processors that sends messages to implement a split lock. Via the messages, the requesting processor is granted exclusive access to the shared memory so that no other processor may access the same data until after the non-atomic operation has completed. The messages used to avoid the deadlock include a split lock request, a lock message, a grant message, a gone idle message and a release idle message. By using the above messages, the system and method of the present invention accepts requests from multiple processors for exclusive access to memory, orders all of the requests, and awards exclusive access to the first processor to make a request. The system can include a cache memory, associated with a requesting processor, which sends a lock request to the main memory in response to a split lock request from a requesting processor.

Abstract: A system and method for enabling a multiprocessor system employing a memory hierarchy to identify data units or locations being used as software locks. The memory hierarchy comprises a main memory having a plurality of data units, a plurality of caches that operate independently of each other, and at least one coherent domain interfaced to each cache. Each coherent domain comprises at least two processors. The main memory maintains coherency of data among the plurality of caches using a directory that maintains information about each data line. The system of the present invention allows a requesting agent, such as a processor or cache, to request a data unit without specifying the type of ownership, where ownership may be exclusive or shared. The directory includes history information that defines the previous access pattern of the requested data unit.

Abstract: A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus.

Abstract: System and method for controlling the flow of messages in a computer system to minimize congestion and prevent deadlocks in communications. The computer system includes a main memory, a plurality of crossbar switches, a plurality of third level caches, and a plurality of input/output modules, which are interconnected via the communications network of the computer system. System and method prevents deadlocks between input/output modules and main memory, and between processors and main memory caused by data needed for making forward progress in processing being trapped behind messages. System and method utilize control signals and auxiliary buffers to hold and redirect messages out of the path of data so that data may flow to the input/output modules and processors when needed, and messages may flow when convenient.

Abstract: Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility.

Abstract: An Input/Output (I/O) subsystem is provided for transferring frames containing frame control data from a serial data transfer medium to a parallel storage medium. The subsystem includes independent components for processing different portions of the received character stream. The subsystem includes a sequence recognition mechanism for receiving and identifying any of a plurality of digital data bit sequences. The sequences represent channel status information from the data transfer medium. The sequence recognition mechanism provides an interrupt signal derived from the sequences. A frame recognition mechanism responds to the interrupt signal. The frame recognition mechanism receives and identifies a start-of-frame delimiter or an end-of-frame delimiter from the data transfer medium. The frame recognition mechanism provides a frame status signal. A frame receiving mechanism responds to the frame status signal. The frame receiving mechanism receives and identifies a frame header from the data transfer medium.

Abstract: Apparatus is provided for use in an Input/Output (I/O) subsystem. The I/O subsystem is coupled to a serial data transfer medium that transmits data from a sender to a recipient. The I/O subsystem processes a frame comprising user defined data and frame control data. The frame is received over the serial data transfer medium. The apparatus includes a mechanism for receiving and validating the frame from the serial data transfer medium. The receiving mechanism transmits the user defined data to a first-in, first-out (FIFO) buffer. A mechanism is provided for forming a block header. The block header comprises control data that are used by the recipient of the user defined data. The block header forming mechanism is distinct from the FIFO buffer. A switching mechanism is coupled to receive the block header and a subset of the user defined data. The recipient has a parallel storage medium.