Abstract: A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.

Abstract: A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.