Abstract: A computer system includes a printed circuit board manufactured in accordance with simulated trace impedances and topologies. The printed circuit board includes trace impedances characterizing at least three dimensions of a multi-dimensional space of the printed circuit board. The printed circuit board design includes trace impedances and topologies obtained with the use of a quasi-Monte Carlo simulation methodology.

Abstract: In electronic equipment, such as, for example, a personal computer printed circuit board, an arrangement for mitigating EMI, noise and other spurious signals at high frequencies. The arrangement includes a discrete capacitor coupled between an active pad and a reference pad. A conductor is coupled to the discrete capacitor and is configured to include a serpentine trace and a terminating tuning capacitance that are effectively series resonant at a predetermined frequency. In an exemplary embodiment, the serpentine trace comprises a number of substantially linear, mutually parallel segments that are joined by turns. The length and width of the serpentine trace, together with the number and spacing of linear segments, cooperates with the geometry of the tuning capacitance to determine the frequency of maximum attenuation of spurious signals.

Abstract: A circuit for detecting ground bounce and for using the detection information to reduce data error resulting therefrom is described. In one embodiment an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event The on-chip logic circuit can be implemented to take a variety of actions upon receipt of notification from the detection circuit that a ground bounce has been detected.

Abstract: A methodology for predicting incidents of ground bounce and using this information for reducing data error caused thereby is described. In one embodiment, data to be clocked into a plurality of output buffers from a first register is read before it goes to the buffers and a determination is made as to what number of bits B will change state, i.e., from a zero to a one or a one to a zero. B is then compared to a predetermined threshold T. If B is greater than T, a wait state or some other indication is issued when the bits are clocked into the I/O buffers.

Abstract: A technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses is described. In one embodiment, the output buffers of an integrated circuit (“IC”) are phased so that half of the buffer outputs are driven first and the remaining half are driven a slight time delay later. The outputs are then de-skewed by package routing so that the earlier signals reach the package pins at the same time as the later signals. This deskewing is accomplished by serpentining and length-matching the bank of non-delayed outputs so that these trace-induced delays match an optimized fixed clock delay used to delay the bank of delayed outputs, the traces of which are length-matched and routed as short as possible.

Abstract: A multi-layer circuit substrate having an integral bus portion includes a dielectric substrate having a first device signal layer formed on a first side thereof and a second device signal layer formed on a second side thereof. The first and second device signal layers are each patterned to include at least one bus reference plane. A device reference plane layer is disposed between the first and second device signal layers in the dielectric substrate. The device reference plane layer is patterned to include a plurality of guard bands and a bus signal trace between at least two of the guard bands.