Patents by Inventor Douglas F. Ridley

Douglas F. Ridley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor device with reduced packaging stress
    Patent number: 5171716
    Abstract: A semiconductor device contains a stress-relief layer (46) having a glass transition temperature below 150.degree. C. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer is preferably made by lithographic patterning.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: December 15, 1992
    Assignee: North American Philips Corp.
    Inventors: Myron R. Cagan, Douglas F. Ridley, Daniel J. Belton
  • Semiconductor device with reduced packaging stress
    Patent number: 5045918
    Abstract: A semiconductor device contains a stress-relief layer (46) having a glass transition temperature of 25.degree. C. or less. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer preferably is a silicone polymer consisting of exposed photosensitive material.
    Type: Grant
    Filed: April 4, 1990
    Date of Patent: September 3, 1991
    Assignee: North American Philips Corp.
    Inventors: Myron R. Cagan, Douglas F. Ridley, Daniel J. Belton
  • Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer
    Patent number: 4569121
    Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.
    Type: Grant
    Filed: March 7, 1983
    Date of Patent: February 11, 1986
    Assignee: Signetics Corporation
    Inventors: Sheldon C. P. Lim, Douglas F. Ridley, Saiyed A. Raza, George W. Conner