Abstract: Some embodiments provide configuration of an internal monitoring mechanism of a processing device to output first data associated with a predetermined operational state of the processing device, and loading of control code into the processing device. The control code may be executable by the processing device to output second data associated with input operations and exceptions that occur during execution of test code by the processing device.

Abstract: Some aspects provide determination of a debug event, selection of a controller context based on the determined debug event, and execution of the selected controller context. The debug event may be associated with a microprocessor, and the controller context may be selected based on predetermined associations between a plurality of debug events and a plurality of controller contexts.

Abstract: Some embodiments provide a device under test comprising a processing core to support execution debug signals, a debug ring to receive and to transmit the execution debug signals from and to the device under test, a first debug port to receive and transmit the execution debug signals from and to the debug ring, and a second debug port to receive data from observation signal lines of the device under test. The first debug port may transmit execution debug signals to define an event to detect within the device under test, to receive execution debug signals indicating occurrence of the event, and to use a handler to place the device under test in a quiescent state and to instruct the device under test to transmit data of one or more registers. The second debug port may receive the data of the one or more registers from observation signal lines of the device under test.

Abstract: Some aspects provide determination of a debug event, selection of a controller context based on the determined debug event, and execution of the selected controller context. The debug event may be associated with a microprocessor, and the controller context may be selected based on predetermined associations between a plurality of debug events and a plurality of controller contexts.

Abstract: A microprocessor system debug tool has a mainframe which interfaces with a user. A ROM emulator replaces a ROM unit of the microprocessor system to be tested and has a monitor portion which is used to perform debug functions specified by the user. A user defined control line is connected to the interrupt system of the microprocessor system to cause the target microprocessor to stop execution of the user's program and jump to the monitor portion upon the occurrence of a user defined event to execute microprocessor specific debug code generated by the mainframe in response to the user's input. At the conclusion of debug code execution the microprocessor resumes the user's program. A word recognizer is connected to the microprocessor bus to detect the results of the debug code execution, the results being forwarded to the mainframe for display to the user.

Abstract: A digital signal sampling system is disclosed for reconstructing the time relationship of digital data signals sampled by two sampling clock signals with different unrelated timebases. The digital data signals sampled may be the same data signal or two different data signals sampled simultaneously in two separate sampler circuits at two different unrelated sampling clock frequencies or timebases to produce first and second sampled data signals. A timebase correlation circuit produces first and second time correlation signals in the form of binary level signals in response to the receipt by a last clock pulse detector of first and second store clock signals which are derived from first and second sampling clock signals. The time correlation signals indicate by their binary level the source of the last previous clock pulse of the first and second store clock signals which was received by the timebase correlation circuit.