Abstract: An optical scanning device performs sequential scanning passes. Individual pixels are scanned in response to a clock whose frequency is dithered in repeatable cycles to reduce electro-magnetic interference, and scanning passes are coordinated with the repeatable cycles.

Abstract: A method and apparatus for handshaking using a 2-wire protocol is described. An electronic component may be divided into blocks, with the blocks performing one or more functions. The blocks may be in series with one another to form a pipeline. The blocks may use interface circuitry to transfer information upstream from or downstream to another block. The interface circuitry uses the 2-wire handshaking for the transfer including a transmit readiness wire configured to carry a signal indicative of readiness of the upstream circuit to output data and a receive readiness wire configured to carry a signal indicative of readiness of the downstream circuit to receive the data.

Abstract: Imaging devices incorporating semi-volatile NAND flash memory are described herein. According to various embodiments, demonstration page information may be stored in the semi-volatile NAND flash memory, which may be reused and incorporated back into the memory pool after the demonstration page information is no longer needed. Other embodiments may be described and claimed.

Abstract: An image processing method and device for processing multiple rows of pixels of an image simultaneously with a single instruction. The processing includes selecting a pixel window having a plurality of pixels of an image spanning across multiple rows and columns, building vertical and horizontal load registers to include the plurality of pixels of the selected pixel window, and simultaneously processing selected pixels of the plurality of pixels included in the vertical and horizontal load registers using a single instruction, wherein the vertical and horizontal load registers are shifted when the selected pixels are processed. Accordingly, a method and device for efficient processing of an image is provided.

Abstract: Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Abstract: Imaging devices incorporating semi-volatile memory are described herein. According to various embodiments, a communication interface may receive image data that is stored in a semi-volatile NAND flash memory device divided into three regions. Other embodiments may be described and claimed.

Abstract: Methods and apparatuses that facilitate the alignment of multiple color planes of a latent image in a multi-beam multi-pass printer are described herein. The novel methods includes determining, during a first pass of a transfer medium of a multi-beam printer, a first time interval between when at least one light beam from a multi-beam device is detected and when a top of a page is detected at a selected location of the transfer medium, the multi-beam device including a plurality of light beam sources, and the first pass to form a first color plane of a latent image on the transfer medium. The methods further include selecting, based at least in part on the determined first time interval, a first one of the plurality of light beam sources to begin illuminating the transfer medium to create the first color plane on the transfer medium during the first pass of the transfer medium.

Abstract: The video data is parallel processed allowing for extremely fast video processing or a greatly reduced clock requirement for the video processing circuit. In operation, each video channel reads from main memory. This allows each video channel to track the laser directly. The Parallel video processor receives non-columnar pixel data, such as rows. The videoprocessor may support printers of any width without significantly increasing the size of the system.

Abstract: The disclosed embodiments relate to a memory controller for retrieving a plurality of data stored in a memory in communication with the memory controller, the plurality of data being characterized by a first arrangement of first and second non-parallel arrays, such as one-dimensional arrays. The first array comprises at least first and second data of the plurality of data and the second array comprises at least the first data and third data of the plurality of data. The memory is operative to provide the at least first and second data of the first array before providing at least the third data of the second array when the memory is accessed based on an address of the first data in the memory and an amount of the plurality of data to provide starting from the address of the first data.

Abstract: A laser scanning assembly generates a laser beam and scans the laser beam through a plurality of scan lines to form desired dots. Each scan line is positioned to overlap an adjacent scan line and each dot includes a plurality of segments. The scanning assembly scans the laser beam through multiple scan lines to fully discharge each segment of each dot. The laser scanner assembly would typically be part of a laser printer.

Abstract: A system is provided for scaling image data comprising a Direct Memory Access (DMA) engine adapted to read the image data from a horizontal pixel strip in a column-by-column format, a scaling block adapted to scale the image data read by the read DMA engine into scaled column output data, and a buffer memory for storing the scaled column output data for the horizontal pixel strip. A method is also provided for scaling an image comprising reading pixel values from a pixel strip in a column-by-column manner across the pixel strip and scaling the pixel values for each column to produce scaled column output data. The scaled column output data for a plurality of columns is then read and the scaled column output data is scaled from the plurality of columns to produce scaled row output data for a row of pixels.

Abstract: A system, method, and processor executable instructions to isochronously communicate in standard USB mode laser printer scan data from a host computer to a laser printer. The host computer transmits a data stream that includes data packets having laser printer scan data, error detection information, and correction packets such as parity packets for use to reconstruct packets having an error. The laser printer receives the data stream, processes the error detection information, data packets and parity packets, and provides a continuous stream of laser printer scan data for printing.

Abstract: A laser print apparatus includes a memory for storing a multi-bit image including a plurality of pixels. Each pixel is represented by an N-bit value, wherein N is greater than one. A modulation code generator analyzes three adjacent pixels. The three adjacent pixels include a left pixel, a center pixel, and a right pixel. The modulation code generator is configured to generate a pulse width value based on the value of the center pixel, and a justification value based on the values of the left pixel and the right pixel. A laser print engine forms an output pixel on media based on the pulse width value and the justification value.

Abstract: A method and apparatus for printing data on a print medium is disclosed. The apparatus is configured to format print data to pixel data, the pixel data including pixel values; identify a grid of pixels having a predetermined pattern of pixel values; obtain predetermined pcode grid from memory for the identified grid of pixels; and send the predetermined pcode grid to controller circuit for printing.

Abstract: Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Abstract: Halftoning apparatus and method that may generate and employ average values and shifts are described herein. The apparatus may include an unpacker to determine shifts and average values for a plurality of input pixel values, each pair of average value and shift being associated with a corresponding pair of the input pixel values. The apparatus may further include a halftone core coupled to the unpacker to receive the shifts and the average values from the unpacker and to generate pairs of output pixel values based at least in part on the received shifts and average values, wherein the output pixel values are for generating pixels of an image.

Abstract: A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control circuitry responsive to data in the plurality of registers. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the parameters of the plurality of registers. At least two consecutive data transactions are executed with respect to non-contiguous system locations.

Abstract: A method and apparatus for performing color plane adjustment are provided. In one embodiment, an apparatus comprises a set of inputs for receiving a first input value and a second input value in a color space. The apparatus also comprises a color plane adjustment component operative to adjust the first input value and the second input value by amounts that depend on a distance of the first input value and second input value, respectively, from a value of neutral gray in the color space. The apparatus further comprises a set of outputs for outputting the adjusted first and second values. A related method and computer program are disclosed. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a periodic authorization signal to cause the memory access controller to remove the inhibition and write a predetermined amount of data to the memory through a data bus, and 2) releasing the data bus following writing of the predetermined amount of data to the memory by inhibiting the memory access controller from writing further data.

Abstract: A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.