Abstract: A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.

Abstract: A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).

Abstract: An interconnect system (31) includes an interconnect bump (29) over an under bump metallurgy (25). The under bump metallurgy (25) includes a barrier layer (26) having a barrier material such as titanium, an adhesion layer (28) having an adhesion material such as copper, and a mixture layer (27) having both the barrier material and the adhesion material. The mixture layer (27) is located between the barrier layer (26) and the adhesion layer (28), and the adhesion layer (28) is located between the mixture layer (27) and the interconnect bump (29). The interconnect bump (29) contains solder and is used as an etch mask when patterning the under bump metallurgy (25).

Abstract: A method for forming an electrical interconnect on a substrate. At least one pad (14) is formed on a substrate (11). The pad (14) is formed having a non-wetting surface (12) and a wettable surface (13). Photoresist (44) is patterned on a substrate (41) forming a cavity on a pad (46) leaving a non-wetting surface (42) and a wettable surface (43) exposed. Interconnect material (56) is formed on a non-wetting surface (52) and a wettable surface (53) of pad 57. Interconnect material (56) is reflowed forming an interconnect ball (74) on a wettable surface (73). Surface tension causes interconnect material (56) when reflowed to flow from a non-wetting surface (72) to the wettable surface (73) and ball up to form the interconnect ball (74).

Abstract: A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.

Abstract: A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.