Abstract: Apparatus, systems, articles of manufacture, and methods to modify sound of speech in an audio signal are disclosed. An example apparatus includes processor circuitry to execute instructions to: identify a first portion of a keyword in the speech of the audio signal during generation of the speech; determine a waveform to replace a second portion of the keyword; and transform the keyword into a different word by introducing the waveform into the audio signal.

Abstract: A system, apparatus, method, and computer program product for a speaking aid. The system including network interface circuitry to receive speech input from a user. The speech input includes a partial sentence with a missing word or the partial sentence with a stuttered word. The system also includes a processor coupled to the network interface circuitry and one or more memory devices coupled to the processor. The one or more memory devices include instructions, that when executed by the processor, cause the system to detect a stutter or pause in the speech input, predict the stuttered word or the missing word, present a predicted word from an n-best list to the user; and if a prompt is received from the user, present a next word from the n-best list until the user speaks a correct word to replace the stutter or the pause.

Abstract: A system, method, apparatus and computer readable medium for hierarchical speech recognition resolution. The method of hierarchical speech recognition resolution on a platform includes receiving a speech stream from a microphone. The speech stream is resolved using a lowest possible level automatic speech recognition (ASR) engine of multi-level ASR engines. The selection of the lowest possible level ASR engine is based on policies defined for the platform. If resolution of the speech stream is rated less than a predetermined confidence level, the resolution of the speech stream is pushed to a next higher-level ASR engine of the multi-level ASR engines until the resolution of the speech stream meets the predetermined confidence level without violating one or more policies.

Abstract: A system, apparatus, method, and computer readable medium for using an audio trigger for surveillance in a security system. The method including receiving an audio input stream via a microphone. Dividing the audio input stream into audio segments. Filtering high energy audio segments from the audio segments. If a high energy audio segment includes speech, then determining if the speech is recognized as the speech of users of the system. If the high energy audio segment does not include the speech, then classifying the high energy audio segment as an interesting sound or an uninteresting sound. Determining whether to turn video on based on classification of the high energy audio segment as the interesting sound, speech recognition of the speech as the speech of the users of the system, and contextual data.

Abstract: A system, apparatus, method, and computer program product for a speaking aid. The system including network interface circuitry to receive speech input from a user. The speech input includes a partial sentence with a missing word or the partial sentence with a stuttered word. The system also includes a processor coupled to the network interface circuitry and one or more memory devices coupled to the processor. The one or more memory devices include instructions, that when executed by the processor, cause the system to detect a stutter or pause in the speech input, predict the stuttered word or the missing word, present a predicted word from an n-best list to the user; and if a prompt is received from the user, present a next word from the n-best list until the user speaks a correct word to replace the stutter or the pause.

Abstract: A system, method, apparatus and computer readable medium for hierarchical speech recognition resolution. The method of hierarchical speech recognition resolution on a platform includes receiving a speech stream from a microphone. The speech stream is resolved using a lowest possible level automatic speech recognition (ASR) engine of multi-level ASR engines. The selection of the lowest possible level ASR engine is based on policies defined for the platform. If resolution of the speech stream is rated less than a predetermined confidence level, the resolution of the speech stream is pushed to a next higher-level ASR engine of the multi-level ASR engines until the resolution of the speech stream meets the predetermined confidence level without violating one or more policies.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for encapsulation of high definition audio data over an input/output interconnect. In some embodiments, a system includes tunneling logic coupled with a high definition (HD) audio controller. The tunneling logic may receive digital audio data from the HD audio controller, encapsulate the digital audio data in a message suitable for an in-band input/output (IO) interconnect, and send the message to an add-in graphics card via the in-band input/output IO interconnect. Other embodiments are described and claimed.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: In one embodiment of the invention, a write cache line with a unique bit pattern is written into memory in a memory channel at a starting address. An attempt is made to enable micro-tile memory accesses into each memory integrated circuit on memory modules in the memory channel. A read cache line is read from memory in the memory channel at the starting address. The bit patterns of the read cache line and the write cache line are compared. If in the comparison it is determined that the bit pattern of the read cache line differs from the write cache line, then micro-tile memory access is enabled into each memory integrated circuit on memory modules in the memory channel. If in the comparison it is determined that the bit pattern of the read cache line is the same as the bit pattern of the write cache line, then micro-tile memory access is not supported and cannot be enabled in each memory integrated circuit on memory modules in the memory channel.

Abstract: In some embodiments input information received at an input device is encrypted before it is sent to a computer to be coupled to the input device. Other embodiments are described and claimed.