Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for operating each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.

Abstract: A method and apparatus for addressing a memory space as a row and column matrix so as to allow the single matrix to store data of various widths, e.g., 16, 32 and 48-bits, with a minimum of wasted memory space. A specified number of the LSBs of the address are used to select a row in the matrix, while the remaining MSBs are used to select a columnar portion. Additional bits indicate the length of the data selected. The MSBs of the address and the additional bits indicating the length of the word accessed are used as inputs to a combinational logic circuit, the outputs of which are coupled to control switches for activating only the appropriate columnar portion of the matrix. Thus, although the LSBs of the address used to select the row activate every bit in that row, the switches are controlled so as to connect to the bus only the bits in that row corresponding to the selected columnar portion.

Abstract: A multi-port RAM register file adapted for flowing data directly from an input port of the register file to an output port of the register file and for simultaneously writing to a memory location in the register file. In addition to the RAM register, the apparatus includes, in a first embodiment, (1) first and second sets of multiplexers, the first set of multiplexers connected between the register file output ports on the one hand, and, on the other hand, the outputs of the second set of multiplexers and the RAM bit lines; the second set of multiplexers being connected between one input of the first set of multiplexers, as aforementioned, and the RAM register file input ports; and (3) flow-through address comparitors for controlling the multiplexers. The bit buses of the RAM are driven directly from the register file input ports.

Abstract: A multiport RAM register file adapted for flowing data directly from an input port to an output port and for simultaneously writing to a location in the register file. In addition to the RAM register, the apparatus includes (1) a first set of multiplexers between the input ports and the RAM, (2) a second set of multiplexers between the output of the RAM and the output ports and (3) logic for controlling the multiplexers and writing to the RAM. The input multiplexers are controlled by flow-through address comparators; the output multiplexers are controlled by read address comparators. The data at any input port of the register file may be written to any of the RAM data bit buses by selecting the input multiplexer appropriately. Because the bit buses are being driven, this data simultaneously may be passed to the RAM output just as if the RAM were being read--i.e., as a flow-through.

Abstract: In a microprogammed controller, the conventional pipeline register is replaced by a pair of coupled latches: a so-called "transparent" latch is placed between the output of the microprogram memory and the input of one or more system resources including at least the sequencer or address generator, and another latch is placed between the output of each such resource and the destination of its output. The appropriate bits of a microinstruction are supplied from the microinstruction memory to the associated resource via the transparent latch. The clock signal for the sequencer or other resource serves as the enable signal for the output latch (which can be either a transparent latch or an edge-triggered latch resposive to the rising edge of the clock signal), while the inverted sense of the clock signal provides the enable signal for the transparent latch.

Abstract: A MOS sense amplifier having a differential input and a single-ended output, and formed of only six MOS transistors. The amplifier's non-inverting input is connected to the gates of first and second MOSFETs. The drains of the first and second MOSFETs are connected to each other and to the gates of third and fourth MOSFETs. The drain of the third MOSFET is connected to the sources of the second and sixth MOSFETs; and the source of the third MOSFET is connected to the positive supply voltage. The drain of the fourth MOSFET is connected to the sources of the first and fifth MOSFETs. The source of the fourth MOSFET is connected to ground. The inverting input of the sense amplifier is connected to the gates of the fifth and sixth MOSFETs. The drains of the fifth and sixth MOSFETs are connected to each other and provide the output terminus of the amplifier. The first, fourth and fifth MOSFETs are n-channel devices, while the second, third and sixth MOSFETs are p-channel devices.