Abstract: Apparatus for sensing a current across a known resistor comprising a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.

Abstract: A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also include any number of intermediate stage clock generators coupled in series between the back end clock generator and the second stage clock generator. Example implementations of the various clock generator stages are also described herein.

Abstract: A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter (“ADC”) is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Abstract: Apparatus for sensing a current across a known resistor comprising a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.

Abstract: A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

Abstract: The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.

Abstract: Apparatus for sensing a current across a known resistor including a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.

Abstract: A pipelined analog to digital converter (“ADC”) as described herein is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase) using isolated input stages. The outputs of the input stages are concurrently sampled (every other clock phase) by a delay/holding and synchronization (“DHS”) stage. The DHS stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The DHS stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Abstract: A method and apparatus are provided for reducing the size and power of cyclic analog-to-digital converter (ADC) conversion circuits. During each cycle, the ADC conversion circuit generates a plurality of bits. The improved ADC includes a scaling/reference circuit having a single operational amplifier which operates in a reference generation mode and an analog multiplexing mode during generation of the first bit and operates in the analog multiplexing mode during generation of the subsequent bits.

Abstract: An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

Abstract: An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

Abstract: An analog-to-digital (A/D) converter suitable for use with redundant signed digit (RSD) coverter stages is provided with an out-of-range (OOR) detection circuit. If an out-of-range input signal is detected, the detection circuit identifies the OOR condition so that the converter can take remedial action. Examples of remedial action may include adjusting the gain of one or more converter stages, adjusting the analog input signal provided to one or more converter stages, and/or adjusting the digital output of the converter to reflect the OOR condition. The ORR detection circuit may receive its input from a converter stage that is distinct from the stage providing the most significant bit (MSB) of the digital output to preserve the resolution of the most significant bit.

Abstract: A low power cyclic RSD analog to digital converter (20) has a single RSD stage (22) that receives one of an analog input signal and a residual voltage feedback signal and converts the one selected signal to a digital output signal. The RSD stage (22) generates the residue voltage feedback signal. A first switch (32) is connected between a converter input terminal (30) and an input terminal of the RSD stage (22) for applying the analog input signal to the RSD stage input terminal. A second switch (52) is connected between an output terminal of the RSD stage (22) and the input terminal of the RSD stage. When the first switch (32) is closed, the second switch (52) is open so that the analog input signal is input to the RSD stage (22), and when the first switch (32) is open, the second switch (52) is closed so that the residual voltage feedback signal is input to the RSD stage (22).

Abstract: A gain stage using switched capacitor architecture and suitable for a pipelined analog to digital converters provides for three pairs of switched capacitor banks whose use may be alternated so as to provide simultaneous sampling of two input channels for sequential gain operation without the interposition of additional circuitry in the signal chain from input to output of the gain stage.

Abstract: A sigma-delta modulator (10) and a method for digitizing an analog signal. The sigma-delta modulator includes at least one switch (16) for altering the order of the sigma-delta modulator (10). The order of the sigma-delta modulator (10) is changed based on the communication protocol of the received analog signal. More particularly, the order of the sigma-delta modulator (10) is increased for communication protocols having wide information-bandwidths. Alternatively, the order of the sigma-delta modulator (10) is decreased for communication protocols having narrow information-bandwidths.

Abstract: A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P.sub.1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V.sub.AGO) during a second clock phase, which increases the output loading during the second clock phase (P.sub.2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P.sub.1) to match the load produced by the refresh circuit (604) during the second clock phase (P.sub.2).

Abstract: A clock circuit for generating alternate clock phases (P.sub.1, P.sub.2) whose trailing edges define sampling points of an analog-to-digital converter (106). Complementary signals (CLOCK0, CLOCK1) are generated from a system clock (F.sub.SYS) and switched through transmission gates (340-341, 342-343) when an enable signal (V.sub.EN) is applied. The system clock (F.sub.SYS) is delayed by a delay circuit (316) to produce the enable signal (V.sub.EN) after the complementary signals (CLOCK0, CLOCK1) are stable, thereby synchronizing the complementary signals (CLOCK0, CLOCK1) with the enable signal (V.sub.EN).

Abstract: A non-inverting, inverting, delayed non-inverting, and delayed inverting non-overlapping clock signal is provided by a non-overlapping clock generator circuit (41, 61). The non-overlapping clock generator circuit (41, 61) increases time for circuit operation by minimizing delays between non-overlapping clock signals and simultaneously transitioning rising edges of clock signals. A non-overlapping clock generation circuit (41) comprises six NOR gates (43-48) and an inverter (42). Three NOR gates form a first delay line (43-45) and the remaining three NOR gates form a second delay line (46-48). The inverter (42) provides an inverted clock signal to the second delay line. A clock signal propagates through one delay line while the other delay line is non-responsive due to a feedback signal from the active delay line.

Abstract: A programmable analog array (10) comprises an array (11) of cells, each cell including analog circuitry (12), a switch control circuit (18), and a digital storage element (16). The switch control circuit (18) receives a clock signal and sequentially configures the circuits within the analog circuitry (12) to realize different circuit functions in accordance with configuration data stored in different digital memory units (17A-17D) within digital storage element (16). During a time interval, the analog signals generated by the analog circuitry (12) before that time interval are stored in an analog storage element (14), which is constructed from a portion of a capacitor network (54) in the analog circuitry (12) and is partitioned into a set of analog memory units (56A-56D). Each analog memory unit (56A-56D) stores the analog signal for a corresponding phase of the clock signal.

Abstract: RSD n-bit analog-to-digital converter (10) receives voltage VIN that is compared to reference voltages VH and VL in the first stage (18). A digital code, representing VIN, is generated at first stage outputs (24, 26). First stage residue voltage V22 is compared to VH and VL in the second stage (30). A digital code generated at the outputs (28, 32) of the second stage, represent residue voltage V22. Residue voltage V22 is recycled through the first and second stages. Upon reaching the n.sup.th conversion bit, residue voltage V22 of the n.sup.th -1 bit is compared to second stage mid-level voltage reference VMID. A digital code generated at the outputs of the second stage represents the n.sup.th -1 bit residue voltage V22. The digital codes are stored in storage elements (34) and added in a binary adder (38) to provide the n-bit representation of VIN.