Abstract: An image enhancement component of an image processing pipeline preferably uses a single lookup table (LUT) to convert M-bit Red (R), Green (G) and Blue (B) values into respective N-bit R, G and B values, where N is greater than M. Preferably, the N-bit values are determined based on the inverse of an algorithm performed upstream of the image enhancement component by an image correction component. The N-bit R, G and B values provide the image with an improved signal-to-noise ratio (SNR).

Abstract: A digital circuit generates very precise clock frequencies for applications that can tolerate a small degree of jitter but require exact long term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: A laser scanning assembly generates a laser beam and scans the laser beam through a plurality of scan lines to form desired dots. Each scan line is positioned to overlap an adjacent scan line and each dot includes a plurality of segments. The scanning assembly scans the laser beam through multiple scan lines to fully discharge each segment of each dot. The laser scanner assembly would typically be part of a laser printer.

Abstract: A method of image-resolution enhancement employing partial-template matching, including storing at least a portion of an image, and selecting from the image a window comprising a plurality of adjacent line segments having pixels, the window including a target pixel. The method also includes comparing the pixels of the window with a template for a partial match, and responsive to a partial match being found, substituting an enhancement pixel for the target pixel. By allowing a partial match for enhancement instead of requiring a 100-percent match of the prior art, the method provides image-resolution enhancement for digital-image data having noise or other errors.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.

Abstract: A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks and a measurement circuit. The measurement circuit is configured to measure internal operating parameters of the integrated circuit to obtain operating parameter data and provide the operating parameter data for evaluation and configuration of the integrated circuit and the logic blocks.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks, a measurement circuit and a control circuit. The measurement circuit is configured to measure operating parameters of the integrated circuit and the logic blocks and provide operating parameter data. The control circuit is configured to receive the operating parameter data, evaluate the operating parameter data to obtain configuration data and configure the integrated circuit with the configuration data.

Abstract: Reset circuitry for an integrated circuit is presented. An internal oscillator produces an oscillating signal upon power-up of the integrated circuit. The internal oscillator is not dependent on signals generated outside the integrated circuit. An electro-static discharge blocker circuit receives an external reset signal generated outside the integrated circuit. The electrostatic discharge blocker circuit utilizes the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset signal.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks, a measurement circuit and a control circuit. The measurement circuit is configured to measure operating parameters of the integrated circuit and the logic blocks and provide operating parameter data. The control circuit is configured to receive the operating parameter data, evaluate the operating parameter data to obtain configuration data and configure the integrated circuit with the configuration data.

Abstract: Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks and a measurement circuit. The measurement circuit is configured to measure internal operating parameters of the integrated circuit to obtain operating parameter data and provide the operating parameter data for evaluation and configuration of the integrated circuit and the logic blocks.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.