Patents by Inventor Douglas Gephardt

Douglas Gephardt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system
    Patent number: 5781187
    Abstract: A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: July 14, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas Gephardt, Rupaka Mahalingaiah
  • Interrupt control architecture for symmetrical multiprocessing system
    Patent number: 5555430
    Abstract: A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: September 10, 1996
    Assignee: Advanced Micro Devices
    Inventors: Douglas Gephardt, Rupaka Mahalingaiah
  • System management interrupt mechanism within a symmetrical multiprocessing system
    Patent number: 5530891
    Abstract: A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: June 25, 1996
    Assignee: Advanced Micro Devices
    Inventor: Douglas Gephardt