Abstract: Edge conduction in a silicon-on-sapphire transistor is minimized by a process which permits precise doping of the edge channel regions of the transistor. The silicon island (19) containing the transistor (24) is precisely doped around its edges by ion implanting an epitaxial silicon layer (13) on a sapphire substrate (11), with an oxide mask (29) covering, with the exception of a narrow peripheral edge (37), the portion of the silicon which is eventually to form the island (19') on which the transistor is to be constructed. The mask (29) is then expanded by the addition of a sleeve (43) to cover the additional peripheral edge region (37) in the silicon. When the silicon is subsequently etched using the expanded oxide pattern 45 as a mask, the periphery of the remaining silicon will be doped to a predetermined depth (37) corresponding to the width of the sleeve (43).