Abstract: An automatic address assignment system has a plurality of I/O devices coupled to a bus. Each device contains a unique machine-readable identifier which is used to select the device for address assignment. The identifier is a binary bit string. Each bit position in the bit string is selected by the host in a serial manner with the host specifying which binary value is being solicited. All devices whose identifier digit matches the solicited value respond positively and remain in contention for address assignment. The other devices will not respond and drop out of contention for address assignment until the sequence is restarted from the first bit. After the bit sequence is completed, the address for that device is bused to the device, and the sequence is restarted from the first bit until all devices have been assigned an address.