Abstract: A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.

Abstract: A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.

Abstract: A method for performing enhanced pattern scanning includes the steps of: providing a three-dimensional memory structure including multiple physical memory elements; compiling multiple programmable finite state machines, each of the programmable finite state machines representing at least one deterministic finite automation data structure, the data structure being distributed over at least a subset of the physical memory elements; configuring a subset of the programmable finite state machines to operate in parallel on a same input data stream, while each of the subset of programmable finite state machines processes a different pattern subset; and providing a local result processor, the local result processor transferring at least a part of a match state from the deterministic finite automation data structures to corresponding registers within the local result processor, the part of the match state being manipulated being based on instructions embedded within the deterministic finite automation data structures.

Abstract: A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.

Abstract: A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Abstract: A method for performing enhanced pattern scanning includes the steps of: providing a three-dimensional memory structure including multiple physical memory elements; compiling multiple programmable finite state machines, each of the programmable finite state machines representing at least one deterministic finite automation data structure, the data structure being distributed over at least a subset of the physical memory elements; configuring a subset of the programmable finite state machines to operate in parallel on a same input data stream, while each of the subset of programmable finite state machines processes a different pattern subset; and providing a local result processor, the local result processor transferring at least a part of a match state from the deterministic finite automation data structures to corresponding registers within the local result processor, the part of the match state being manipulated being based on instructions embedded within the deterministic finite automation data structures.

Abstract: A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Abstract: A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.

Abstract: According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.

Abstract: A communications parallel bus receiver interface having N data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. An input switching network is configured to receive and couple N parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two adjacent bit receivers. A calibration device calibrates one of the two adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through each of N+1 receivers to periodically recalibrate each receiver (one at a time) while N inputs are processed continuously and uninterrupted.

Abstract: Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.

Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.

Abstract: According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.

Abstract: A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Abstract: A communications parallel bus receiver interface having N data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. An input switching network is configured to receive and couple N parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two adjacent bit receivers. A calibration device calibrates one of the two adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through each of N+1 receivers to periodically recalibrate each receiver (one at a time) while N inputs are processed continuously and uninterrupted.

Abstract: A task obtained by a communications processor is decomposed into one or more requests that form a request group. The requests of the request group are sent to main memory and responses to those requests are expected. There may be requests for a plurality of request groups being processed concurrently. However, responses to the request groups are to be returned to the communications processor in the order in which the request groups were sent from the communications processor. To ensure this ordering, dependencies between the request groups are tracked by hardware coupled to the communications processor.

Abstract: A mechanism for offloading the management of receive queues in a split (e.g. split socket, split iSCSI, split DAFS) stack environment, including efficient queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates receive work queues and completion queues that are utilized by an Internet Protocol Suite Offload Engine (IPSOE) and the ULP to transfer information and carry out send operations. As consumers initiate receive operations, receive work queue entries (RWQEs) are created by the ULP and written to the receive work queue (RWQ). The ISPOE is notified of a new entry to the RWQ and it subsequently reads this entry that contains pointers to the data that is to be received. After the data is received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the RWQ and CQ.

Abstract: A mechanism for offloading the management of send queues in a split socket stack environment, including efficient split socket queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates send work queue entries (SWQEs) for writing to the send work queue (SWQ). The Internet Protocol Suite Offload Engine (IPSOE) is notified of a new entry to the SWQ and it subsequently reads this entry that contains pointers to the data that is to be transmitted. After the data is transmitted and acknowledgments are received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). The flow control between the ULP and the IPSOE is credit based. The passing of CQ credits is the only explicit mechanism required to manage flow control of both the SWQ and the CQ between the ULP and the IPSOE.

Abstract: A task obtained by a communications processor is decomposed into one or more requests that form a request group. The requests of the request group are sent to main memory and responses to those requests are expected. There may be requests for a plurality of request groups being processed concurrently. However, responses to the request groups are to be returned to the communications processor in the order in which the request groups were sent from the communications processor. To ensure this ordering, dependencies between the request groups are tracked by hardware coupled to the communications processor.