Abstract: A non-aligned double word fetch buffer is integrated into a digital signal processor to handle non-aligned double word (32 bit) fetches. When a misaligned double word fetch is detected, the buffer causes a two cycle non-interruptable instruction to be initiated. The first cycle is a 16-bit misaligned data fetch. The address pointer is incremented by 2 and stored in a temporary pointer register. The second cycle is a 32-bit double word fetch based on the temporary pointer with its least significant bit set to 0 (an aligned fetch). The low word from this fetch is used to satisfy the current misaligned double word fetch and the high word is stored in a temporary buffer register in case it proves useful in subsequent misaligned double fetch instructions. Finally, the temporary address pointer is incremented by 2 for possible use in subsequent misaligned fetches.

Abstract: A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer.

Abstract: Apparatus for arbitrating the selection of an interrupt for servicing from a plurality of interrupts in which a priority level for each of the plurality of interrupts is programmed in a first register and each of the interrupts which is to be evaluated for selection for servicing is set as pending in a second register. Only a pending interrupt having a priority level above a pre-set current interrupt priority level is selected for servicing and where multiple pending interrupts of the same priority level occur, the one with the highest order bit position in the second register is used.