Abstract: A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals.

Abstract: A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals.

Abstract: A system for generating a false target radar image for countering wideband synthetic aperture and inverse synthetic aperture imaging radar systems to prevent a selected target from being detected by such radar systems comprises a receiver system for producing a digital signal that represents an incident radar signal. A phase sampling circuit is connected to the receiver for sampling the digital signal and providing phase sample data. An image synthesizer circuit is connected to the phase sampling circuit and arranged to receive the phase sample data therefrom. The digital image synthesizer circuit is arranged to process the phase sample data to form a false target signal, which is input to a signal transmitter system arranged to transmit the synthesized false target signal so that it can be received by a radar system.

Abstract: A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication processes has a precharge transistor connected between a precharge volt source and an output node of the logic circuit. The precharge transistor is controlled by a clock signal such that the output node precharges when the clock signal is low and is isolated from the precharge voltage source when the clock signal is high. An evaluate transistor connected to the output node and an NFET logic block has a first terminal connected to the evaluate transistor such that the evaluate transistor is between the NFET logic block and the output node. A second terminal of the logic block is connected to a voltage source and a data input terminal that is arranged to receive data input signals. The NFET logic block includes on or more transistor(s) is arranged to generate a logic value.

Abstract: A predictive read cache reduces primary cache miss latency in a microprocessor system that includes a microprocessor, a main memory and a primary cache memory connected between the main memory and the microprocessor via an instruction address bus, a data address bus and a data bus. The predictive read cache tracks the pattern of data read addresses that cause misses in the primary cache and associates the pattern with the specific instruction that generates the pattern of miss addresses. When a pattern has been determined, the address where the next cache data read miss will occur is predicted and sent to memory at a time when the memory is not busy with other transactions. The data at the predicted miss address is then fetched and stored in the predictive read cache.

Abstract: A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication rocesses has a precharge transistor connected between a precharge voltage source and an output node of the logic circuit. The precharge transistor is controlled by a clock signal such that the output node precharges when the clock signal is low and is isolated from the precharge voltage source when the clock signal is high. An evaluate transistor connected to the output node and an NFET logic block has a first terminal connected to the evaluate transistor such that the evaluate transistor is between the NFET logic block and the output node. A second terminal of the logic block is connected to a voltage source and a data input terminal that is arranged to receive data input signals. The NFET logic block includes on or more transistor(s) is arranged to generate a logic value.