Patents by Inventor Douglas John Downey

Douglas John Downey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Run-to-run control process for controlling critical dimensions
    Patent number: 5926690
    Abstract: It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist etch time as a manipulated variable.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: July 20, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony John Toprac, Douglas John Downey, Subhash Gupta
  • Run to run control process for controlling critical dimensions
    Patent number: RE39518
    Abstract: It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: March 13, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony John Toprac, Douglas John Downey, Subhash Gupta