Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

Abstract: An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

Abstract: Control a coarse grained reconfigurable array during execution of an assembly language program identifying data flows through memory locations represented by memory variables. For example, a lowering program can be configured to receive the assembly language program, a hardware profile of the coarse grained reconfigurable array, and an instruction execution schedule to generate a configuration usable to control the coarse grained reconfigurable array. The lowering program can identify tile memories used to implement the memory locations represented by the memory variables in the assembly language program, and trace the data flows specified in the assembly language program. Using timing of instruction execution identified in the schedule, the lowering program can determine timing and controls for the dispatch interface, memory interfaces, and internal connections within tiles of the coarse grained reconfigurable array during execution of the assembly language program.