Patents by Inventor Douglas Laird

Douglas Laird has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140100215
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Application
    Filed: December 7, 2013
    Publication date: April 10, 2014
    Applicant: Exelixis, Inc.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Patent number: 8642584
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Exelixis, Inc.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Publication number: 20120302545
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Applicant: Exelixis, Inc.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Publication number: 20100075947
    Abstract: The invention provides methods of treating cancer with a combination of compounds which inhibit kinases, more specifically MEK and PI3K.
    Type: Application
    Filed: August 16, 2007
    Publication date: March 25, 2010
    Applicant: EXELIXIS, INC.
    Inventors: Dana T. Aftab, A. Douglas Laird, Peter Lamb, Jean-Francois A. Martini
  • Patent number: 7557605
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: July 7, 2009
    Assignee: Cswitch Corporation
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
  • Publication number: 20090072858
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: CSWITCH CORPORATION
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
  • Patent number: 5180937
    Abstract: A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: January 19, 1993
    Assignee: LSI Logic Corporation
    Inventors: Douglas Laird, Godfrey P. D'Souza
  • Patent number: 5058110
    Abstract: A computer network method and apparatus. The present invention comprises a computer network having one or more hubs, each hub comprising one or more connection means for connection of computing devices to the network. Each connection means comprising a first interface means for coupling with a computing device, a second interface means for coupling with the network and a protocol processing means. The protocol processing means receives message packets and, depending on the message type, processing the message as either a network control message or a data transfer message. The present invention provides for "flow through" of data in the case of data transfer messages. The present invention further provides for calculation of checksum bytes as a data packet is received by the protocol processing means.
    Type: Grant
    Filed: May 3, 1989
    Date of Patent: October 15, 1991
    Assignee: Ultra Network Technologies
    Inventors: Robert Beach, Mark Bryers, Casey Cox, Richard Fall, Norman Finn, Douglas Laird