Abstract: The present invention relates to a Urinary Incontinence Threshold Device (UITD) which encircles and applies pressure to a penis to stop urine flow. This is accomplished by an upper and lower member held together by O-rings on each side of the device. Pressure is applied to the penis by a disc attached to a threaded rod that passes through an adjusting nut located in the center of the upper member. By turning the adjusting nut, the pressure disc is raised or lowered changing the pressure being applied. Catches and latches attached to each side of the UITD allow the unit to be in a hold-open position for ease of installation. After installation, the latches are released by sequentially applying a diagonal force to opposing corners of the UITD. Scales located on each side of the UITD indicate the amount of pressure being applied to the penis.

Abstract: A trailer-coupling assembly is described for securing a trailer to a two-wheel vehicle. The trailer-coupling assembly is rigidly fixed to a rear-wheel frame of a two-wheel vehicle and the utility bed of a trailer. The trailer-coupling assembly is comprised of three joints that each rotate about three separate cardinal axes, permitting the trailer to navigate rough terrain without transferring rotational loading to the two-wheel vehicle. Each joint is configured to rotate at least 90 degrees in a clockwise direction and an anti-clockwise direction about a cardinal axis, providing the trailer-coupling assembly with flexibility to navigate the two-wheel vehicle and trailer over various grades of rough terrain.

Abstract: A trailer-coupling assembly is described for securing a trailer to a two-wheel vehicle. The trailer-coupling assembly is rigidly fixed to a rear-wheel frame of a two-wheel vehicle and the utility bed of a trailer. The trailer-coupling assembly is comprised of three joints that each rotate about three separate cardinal axes, permitting the trailer to navigate rough terrain without transferring rotational loading to the two-wheel vehicle. Each joint is configured to rotate at least 90 degrees in a clockwise direction and an anti-clockwise direction about a cardinal axis, providing the trailer-coupling assembly with flexibility to navigate the two-wheel vehicle and trailer over various grades of rough terrain.

Abstract: A mounting assembly for an electronic device associated with a machine includes a housing including an interior space adapted to receive the one or more components of the electronic device. The mounting assembly also includes a housing printed circuit board having a first row of pins and a second row of pins. The mounting assembly further includes a harness for allowing interface between the electronic device and the machine. The harness is configured to be connected to the housing in a first orientation or a second orientation. The harness includes a cable and a connecting member provided at one end of the cable. The harness also includes a harness printed circuit board having a first row of pins and a second row of pins. The harness printed circuit board is configured to connect with the housing printed circuit board in any one of the first orientation or the second orientation.

Abstract: An electron beam apparatus addresses blanking issues resulting from sinking high-power heat onto an aperture diaphragm by evenly spreading heat on the aperture diaphragm. The apparatus can include an aperture diaphragm and a deflector that deflects the electron beam on the aperture diaphragm. The electron beam is directed at the aperture diaphragm in a pattern around the aperture. The pattern may be a circle, square, or polygon. The pattern also may include a variable locus relative to the aperture.

Abstract: An electron beam apparatus addresses blanking issues resulting from sinking high-power heat onto an aperture diaphragm by evenly spreading heat on the aperture diaphragm. The apparatus can include an aperture diaphragm and a deflector that deflects the electron beam on the aperture diaphragm. The electron beam is directed at the aperture diaphragm in a pattern around the aperture. The pattern may be a circle, square, or polygon. The pattern also may include a variable locus relative to the aperture.

Abstract: In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.

Abstract: Human interferon-? protein analogs in which the asparagine at position 25, numbered in accordance with native human interferon-?, is recombinantly replaced with an aspartate residue exhibit a biological activity of human interferon-? (e.g. IFN-? 1b) at an increased level relative to IFN-? 1b. These analogs are obtained by introducing a gene coding for Asp25 IFN-? into a cell and expressing the recombinant protein. The resulting IFN-? protein analog is suitable for large scale manufacturing for incorporation in HA-containing or HA-free therapeutics for treatment of diseases including multiple sclerosis. A reduced Lys endoproteinase-C peptide map technique that produces a fingerprint profile for proteins using an enzymatic digest followed by RP-HPLC is also useful in quality control as an ID test for the IFN-? protein analog products.

Abstract: In an embodiment of the invention, a method for lazy signal blocking, includes: when a program is going to enter a critical region of code where signals will be blocked, then setting an enabled flag and marking a signal mask with signals to be blocked, wherein the enabled flag and the signal mask are in a memory address space of the program; and when the program has left the critical region of code where signals will be blocked, then clearing the enabled flag.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.

Abstract: In an embodiment of the invention, a method for lazy signal blocking, includes: when a program is going to enter a critical region of code where signals will be blocked, then setting an enabled flag and marking a signal mask with signals to be blocked, wherein the enabled flag and the signal mask are in a memory address space of the program; and when the program has left the critical region of code where signals will be blocked, then clearing the enabled flag.

Abstract: In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.

Abstract: A method, system and apparatus for selective macro event recording. In accordance with the present invention, events can be selectively included in a macro recording process, even where the events occur across different contexts such as different application windows in different applications. Specifically, once a macro recording session has been initiated for a particular application or application window, events occurring in different applications or application windows can be selected for inclusion in the macro through an append recording operation. Notably, the selective macro recording facility can be included as part of an operating environment, or as part of the individual applications executing within the operating environment.

Abstract: In a memory hub system, several daisy-chained memory hubs are connected to a single memory controller. The memory hub transmitters and receivers operate in a high-speed clock domain, while the logic cores of the memory hubs operate in a low-speed clock domain. A clock domain interface advantageously provides data storage and transfer between the two clock domains without stalling the logic in the low-speed clock domain and without interrupting data movement in the high-speed clock domain.

Abstract: Systems, methods, and devices are provided for time measurement. One embodiment includes a method for measuring time on multiprocessor systems. The method includes allocating a memory space to a thread to be used to communicate with an operating system and saving a context switch count, an offset, and a scale factor, received from the operating system, in the memory space.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.

Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Abstract: A method of allocating memory operates to avoid overlapping hot spots in cache that can ordinarily cause cache thrashing. This method includes steps of determining a spacer size, reserving a spacer block of memory from a memory pool, and allocating memory at a location following the spacer block. In an alternative embodiment, the spacer size is determined randomly in a range of allowable spacer size. In other alternative embodiments, spacers are allocated based upon size of a previously allocated memory block.