Abstract: A system and method for providing a software trap and patch function to low power, cost conscious, and space constrained applications. When a programming error in a first memory is discovered, a data structure comprising a trap address, patch code, and patch address are stored in a second memory. A power-on-reset process detects the presence of the data structure, and in response thereto, enables the trap and patch function. In operation, upon the occurrence of a trap condition, the first memory is disconnected from the data bus and a predetermined instruction circuit is activated. Upon activation thereof, the predetermined instruction circuit, which comprises solely combinational circuitry, places the op code of the predetermined instruction on the data bus. In one embodiment, in which the predetermined instruction is a software interrupt instruction, a predetermined bit of the PSR is placed in a defined state responsive to the occurrence of a trap condition.

Abstract: A method for configuring a program-controlled integrated circuit which contains default configuration data and includes input/output lines connectable to at least one external source of configuration data, the method including: a) determining whether an external source of configuration data is connected to the input/output lines; b) in response to a determination that an external source of configuration data is connected to the input/output lines, configuring the integrated circuit in accordance with that configuration data from that source; and c) in response to a determination that an external source of configuration data is not connected to the input/output lines, configuring the integrated circuit in accordance with the default configuration data.

Abstract: A method for testing a communication link between first and second components of a system, which components communicate via a selected one of a plurality of broadcast channels, the second component being powered by a self-contained power source, the method comprising: causing the first component to scan a plurality of the broadcast channels in sequence in a receiving mode during a scanning period and to broadcast a test signal over the selected channel during the scan; and maintaining the second component in an inactive state in which energy consumption is minimized and in which the second component is unresponsive to broadcast signals during a major part of the scanning period, placing the second component in an active state in which the second component can detect the test signal during a time when the test signal is being broadcast, and causing the second component to broadcast a response signal upon detection of the test signal.