Abstract: An approach is provided for preventing access to mis=plugged devices by a service processor (SP). The SP retrieves an expected device identifier of a device associated with a hot-plug event. The hot-plug event was received in response to the device being connected to a selected port of a service processor, and the port is one many ports included in the SP. The SP sends a request for a device identifier via the port and actual device identifier is received from the device. The device is validated by comparing the expected device identifier with the actual device identifier. If the identifiers match, a link between the SP and the device is maintained. On the other hand, if the identifiers do not match, the link between the SP and the device is terminated or otherwise inhibited.

Abstract: An approach is provided for preventing access to mis=plugged devices by a service processor (SP). The SP retrieves an expected device identifier of a device associated with a hot-plug event. The hot-plug event was received in response to the device being connected to a selected port of a service processor, and the port is one many ports included in the SP. The SP sends a request for a device identifier via the port and actual device identifier is received from the device. The device is validated by comparing the expected device identifier with the actual device identifier. If the identifiers match, a link between the SP and the device is maintained. On the other hand, if the identifiers do not match, the link between the SP and the device is terminated or otherwise inhibited.

Abstract: Fault isolation for a computer system having multiple FRUs in an FSI chain uses logic embedded in a device driver to determine first failure data and a logical error identifier. The logical error identifier represents a hardware logical area of the fault. The fault is then mapped to a segment of the system based on a self-describing system model which includes FRU boundary relationships for the devices. Operation of the device driver is carried out by a flexible service processor. The device driver uses the first failure data to identify a link at a failure point corresponding to the fault and determine a failure type at the link, then maps the link and the failure type to the logical error identifier. After identifying the segment, the device driver can generate a list of callouts of the field replaceable units associated with the segment which require replacement.

Abstract: Fault isolation for a computer system having multiple FRUs in an FSI chain uses logic embedded in a device driver to determine first failure data and a logical error identifier. The logical error identifier represents a hardware logical area of the fault. The fault is then mapped to a segment of the system based on a self-describing system model which includes FRU boundary relationships for the devices. Operation of the device driver is carried out by a flexible service processor. The device driver uses the first failure data to identify a link at a failure point corresponding to the fault and determine a failure type at the link, then maps the link and the failure type to the logical error identifier. After identifying the segment, the device driver can generate a list of callouts of the field replaceable units associated with the segment which require replacement.

Abstract: Fault isolation for a computer system having multiple FRUs in an FSI chain uses logic embedded in a device driver to determine first failure data and a logical error identifier. The logical error identifier represents a hardware logical area of the fault. The fault is then mapped to a segment of the system based on a self-describing system model which includes FRU boundary relationships for the devices. Operation of the device driver is carried out by a flexible service processor. The device driver uses the first failure data to identify a link at a failure point corresponding to the fault and determine a failure type at the link, then maps the link and the failure type to the logical error identifier. After identifying the segment, the device driver can generate a list of callouts of the field replaceable units associated with the segment which require replacement.

Abstract: Fault isolation for a computer system having multiple FRUs in an FSI chain uses logic embedded in a device driver to determine first failure data and a logical error identifier. The logical error identifier represents a hardware logical area of the fault. The fault is then mapped to a segment of the system based on a self-describing system model which includes FRU boundary relationships for the devices. Operation of the device driver is carried out by a flexible service processor. The device driver uses the first failure data to identify a link at a failure point corresponding to the fault and determine a failure type at the link, then maps the link and the failure type to the logical error identifier. After identifying the segment, the device driver can generate a list of callouts of the field replaceable units associated with the segment which require replacement.

Abstract: A system and method are directed towards a pseudo multi-master operation on a serial bus. The pseudo multi-master operation allows multiple devices without standard multi-master functionality to operate on the serial bus as masters. In a disclosed example, the serial bus is an Inter-Integrated Circuit (I2C) bus, which is isolated when an adapter card requires access to the I2C bus, such as to update vital product data (VPD) to a memory device, and to cache the updated VPD to a chassis management module.

Abstract: A method for maintaining vital product data (VPD) of each field replaceable unit (FRUs) in a computer system, the computer system including a first FRU and a second FRU operatively coupled with the first FRU. The method includes calculating a parity for the VPD of the second FRU, and upon detecting a failure of the second FRU, regenerating the VPD for the failed second FRU using the parity.

Abstract: A method for maintaining vital product data (VPD) contained in an EEPROM (Electrically Erasable Programmable Read-Only Memory) on a field replaceable unit (FRU) of a computer system that has a cache. The method includes maintaining a copy of the VPD in the cache, retrieving the copy of the VPD from the cache upon receiving a read request of the VPD, and, upon receiving a write request to write data to the VPD, writing the data to the copy of the VPD, determining whether the VPD in the EEPROM is in synchronization with the copy of the VPD in the cache, and, if the VPD and the copy of the VPD are in synchronization, writing the data to the EEPROM.

Abstract: A system and method are directed towards a pseudo multi-master operation on a serial bus. The pseudo multi-master operation allows multiple devices without standard multi-master functionality to operate on the serial bus as masters. In a disclosed example, the serial bus is an Inter-Integrated Circuit (I2C) bus, which is isolated when an adapter card requires access to the I2C bus, such as to update vital product data (VPD) to a memory device, and to cache the updated VPD to a chassis management module.

Abstract: Selectively recollecting vital product data during an initial program load at data processing system power on is provided. In response to receiving an input to power on a data processing system, a resource location code array table is accessed within a set of selected tables for the data processing system based on machine type. The selected set of tables is located in firmware within a service processor. An entry for a resource in the resource location code array table is read to determine whether the entry includes a no recollect tag. Then, in response to determining that the entry for the resource in the resource location code array table does include a no recollect tag, vital product data for the resource is not recollected during the initial program load.

Abstract: A method for maintaining vital product data (VPD) of each field replaceable unit (FRUs) in a computer system, the computer system including a first FRU and a second FRU operatively coupled with the first FRU. The method includes calculating a parity for the VPD of the second FRU, and upon detecting a failure of the second FRU, regenerating the VPD for the failed second FRU using the parity.

Abstract: A method for maintaining vital product data (VPD) contained in an EEPROM (Electrically Erasable Programmable Read-Only Memory) on a field replaceable unit (FRU) of a computer system that has a cache. The method includes maintaining a copy of the VPD in the cache, retrieving the copy of the VPD from the cache upon receiving a read request of the VPD, and, upon receiving a write request to write data to the VPD, writing the data to the copy of the VPD, determining whether the VPD in the EEPROM is in synchronization with the copy of the VPD in the cache, and, if the VPD and the copy of the VPD are in synchronization, writing the data to the EEPROM.

Abstract: A system for selectively recollecting vital product data during an initial program load at data processing system power on. In response to receiving an input to power on a data processing system, a resource location code array table is accessed within a set of selected tables for the data processing system based on machine type. The selected set of tables is located in firmware within a service processor. An entry for a resource in the resource location code array table is read to determine whether the entry includes a no recollect tag. Then, in response to determining that the entry for the resource in the resource location code array table does include a no recollect tag, vital product data for the resource is not recollected during the initial program load.

Abstract: A method for coupling a collection of master devices on an Inter-Integrated Circuit (IIC) bus, where the collection of master devices includes at least one resident master device, generating a periodic, fixed interval tenure on the IIC bus, synchronizing at least one additional master device with the periodic, fixed interval tenure to enable the at least one additional master device to communicate on the IIC bus, and tuning a period value corresponding to a frequency of the periodic, fixed interval tenure to optimize the synchronizing, wherein the tuning further includes adjusting the period value to vary the frequency of the periodic, fixed interval tenure to balance between available IIC bus bandwidth and synchronization of the at least one additional master device.