Patents by Inventor Douglas M. Grant
Douglas M. Grant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9082633Abstract: An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.Type: GrantFiled: October 13, 2011Date of Patent: July 14, 2015Assignee: XILINX, INC.Inventor: Douglas M. Grant
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Patent number: 8745465Abstract: Methods and circuits detect a burst error in a block of data bits. Coset calculator circuits calculate coset leaders from a syndrome generated from the data bits of the block. The coset calculator circuits calculate the coset leaders for each frame of the data bits. For each frame, comparator circuits input a corresponding coset leader of the coset leaders. Each comparator circuit determines, for each burst-length portion of one or more burst-length portions within the corresponding coset leader, whether the coset bits of the corresponding coset leader are zero except for the coset bits within the burst-length portion. An error-locator circuit outputs an error vector describing the burst error in the block in response to one of the comparator circuits determining that the coset bits of the corresponding coset leader are zero except for the coset bits within one of the burst-length portions within the corresponding coset leader.Type: GrantFiled: July 27, 2011Date of Patent: June 3, 2014Assignee: Xilinx, Inc.Inventors: Heramba Aligave, Douglas M. Grant, Sarvendra Govindammagari
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Publication number: 20130093074Abstract: An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: Xilinx, Inc.Inventor: Douglas M. Grant
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Patent number: 8384568Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.Type: GrantFiled: July 27, 2011Date of Patent: February 26, 2013Assignee: Xilinx, Inc.Inventors: Sarvendra Govindammagari, Veerender Kumar Soma, Heramba Aligave, Douglas M. Grant
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Publication number: 20130027228Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: XILINX, INC.Inventors: Sarvendra Govindammagari, Veerender Kumar Soma, Heramba Aligave, Douglas M. Grant
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Patent number: 7991937Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable circuitry is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath is configured to operate at two frequencies to accommodate the programmable circuitry in the integrated circuit.Type: GrantFiled: October 31, 2008Date of Patent: August 2, 2011Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
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Patent number: 7934038Abstract: A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer interface, programmable resources coupled to the embedded controller via a client interface, tie-off pin inputs coupled to the embedded controller for receiving a configuration vector for configuring the embedded controller without having to use a microprocessor for such configuration with the client interface being for communication between the embedded controller and the programmable resources for access to and from the network, and the embedded controller including a multi-mode interface coupled to the client interface for coupling to the programmable resources, the multi-mode interface including a plurality of Media Independent Interface modes, the multi-mode interface configured to be coupled to the physical layer interface.Type: GrantFiled: July 25, 2008Date of Patent: April 26, 2011Assignee: Xilinx, Inc.Inventors: Ting Yun Kao, Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards, Allan W. Fyfe
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Patent number: 7840921Abstract: A method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.Type: GrantFiled: March 20, 2008Date of Patent: November 23, 2010Assignee: Xilinx, Inc.Inventor: Douglas M. Grant
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Patent number: 7814446Abstract: A method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.Type: GrantFiled: March 20, 2008Date of Patent: October 12, 2010Assignee: Xilinx, Inc.Inventor: Douglas M. Grant
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Patent number: 7761643Abstract: A media access controller system embedded in an integrated circuit is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in an integrated circuit. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.Type: GrantFiled: January 12, 2009Date of Patent: July 20, 2010Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
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Patent number: 7493511Abstract: A transmit-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a transmit engine. A transmit-side datapath is coupled to the media access controller core. The transmit-side datapath is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.Type: GrantFiled: January 21, 2005Date of Patent: February 17, 2009Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
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Patent number: 7484022Abstract: A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.Type: GrantFiled: January 21, 2005Date of Patent: January 27, 2009Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
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Patent number: 7461193Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath configured is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.Type: GrantFiled: January 21, 2005Date of Patent: December 2, 2008Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
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Patent number: 7421528Abstract: A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.Type: GrantFiled: October 31, 2006Date of Patent: September 2, 2008Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant
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Patent number: 7376929Abstract: Method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.Type: GrantFiled: November 10, 2004Date of Patent: May 20, 2008Assignee: Xilinx, Inc.Inventor: Douglas M. Grant
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Patent number: 7366807Abstract: A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.Type: GrantFiled: January 21, 2005Date of Patent: April 29, 2008Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant, Stuart A. Nisbet, Gareth D. Edwards
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Patent number: 7143218Abstract: Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block) located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.Type: GrantFiled: January 21, 2005Date of Patent: November 28, 2006Assignee: Xilinx, Inc.Inventors: Robert Yin, Hamish T. Fallside, Richard P. Burnley, Nicholas McKay, Martin B. Rhodes, Douglas M. Grant
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Patent number: 5971595Abstract: A method and system for converting a hardware description language file which includes parameterized attributes into a product specification with hardware properties generated based on the parameters used to create/instantiate cells defined by the hardware description language file. The hardware properties are used by design tools to perform such functions as pre-place cells, route cells, and control the configuration of cells.Type: GrantFiled: April 28, 1997Date of Patent: October 26, 1999Assignee: Xilinx, Inc.Inventors: Douglas M. Grant, John P. Gray
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Patent number: 5828588Abstract: A parametrizable control module comprising first and second loadable counters, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit.A parametrizable control module comprises a first and a second loadable counter. Both counters are fed by a primary clock input. The first counter feeds an enable input of the second counter. An output of the second counter feeds a module output. Furthermore, both counter outputs by means of a logical combining gate feed the enable input of the second counter as well as the module output. The module has a reset input that feeds the reset inputs of both counters and the enabling input of the second counter. The parametrizable control module is useful for multiple application in a controller circuit. Also a method for synthesizing such circuits is given.Type: GrantFiled: November 25, 1996Date of Patent: October 27, 1998Assignee: U.S. Philips CorporationInventor: Douglas M. Grant
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Patent number: 4415011Abstract: To collect a series of liquid samples each of which has a fixed volume in a corresponding series of sample bottles, a sample collector includes a control circuit that initiates the sampling at preset time intervals or each time a preset volume of liquid has flowed past the collector as indicated by a flow meter. To control the volume of each sample, an optical liquid interface detector within the flow passage of the sample collector initiates counting of the revolutions of the pump and after a pre-selected number of counts, the control circuit terminates the pumping. The optical liquid interface detector includes a light-emitting diode on one side of the flow passage and a phototransistor on the opposite side to detect the interface of the liquid.Type: GrantFiled: November 2, 1981Date of Patent: November 15, 1983Assignee: ISCO, Inc.Inventor: Douglas M. Grant