Patents by Inventor Douglas M. Hannan

Douglas M. Hannan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6590435
    Abstract: A method and apparatus that restrict the differential output voltage (VOD) for an LVDS input buffer is provided. Specifically, VOD is prevented from exceeding a predetermined threshold. The input and output common-mode voltage, as well as the input and output differential voltage swing, are maintained during the VOD restriction. The VOD restriction reduces output jitter of the LVDS input buffer and provides a more robust LVDS system as compared to an LVDS system not using a VOD restriction circuit. Clamping circuits are used to restrict the VOD. Each half of the differential output voltage may be clamped to restrict the differential output voltage. The clamping circuits are activated in response to the VOD reaching the predetermined threshold. When a clamping circuit is active, an alternate current path is provided maintaining the level of the signal before clamping.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: July 8, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Douglas M. Hannan, David J. Haas
  • Patent number: 6529043
    Abstract: The present invention provides a method and apparatus for current steering for an LVDS input buffer. A current steering circuit is configured to steer current to a first node and/or a second node in response to a comparison between the input common-mode signal and a reference signal. During high input common-mode, more current is steered to the P-channel differential pair node of the input buffer as compared to the N-channel differential pair node. During low input common-mode, more current is steered to the N-channel differential pair node of the input buffer as compared to the P-channel differential pair node. The current steering reduces jitter and achieves stable output of the input buffer over process, voltage and temperature. The method and apparatus provided ensures a stabilized summation of the currents ID1+ID3 and ID2+ID4 by steering current into the P-channel node or N-channel node.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: March 4, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Douglas M. Hannan