Abstract: A circuit and process for controlling access to a digital storage device is disclosed. The process involves reading a control word from a control store and partially decoding an address field of the control word to predict the storage location to be accessed. The address field is subsequently fully decoded to determine the actual storage location to be accessed. Prior to completion of this decoding step, an access to the predicted location in main storage is initiated. In the event the actual storage location to be accessed differs from the predicted one, the memory access previously initiated is overridden and an access to the actual storage location is initiated. A digital compouter system incorporating a circuit for carrying out this process exhibited significantly reduced running times for typical computer programs.

Abstract: Address translation apparatus is provided where the address to be translated is compared with two address translation candidates sequentially. The virtual address to be translated is contained in a virtual address register. A field of bits within the virtual address are presented simultaneously as an address to a translation table and a pre-translation table where the pre-translation table has two entries per row and each entry contains some of the virtual address bits of corresponding candidates in the translation table. The pre-translation table is quite narrow compared to the translation table and is preferably, but not necessarily, implemented in latches or as a very fast array compared to the translation table.