Abstract: Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

Abstract: A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

Abstract: An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.

Abstract: A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one TSV (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die. The solar cell die is configured to power the circuitry die. The solar cell die includes a transparent contact on a front side of the solar cell die. A back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die.

Abstract: A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.

Abstract: A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

Abstract: A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

Abstract: This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.

Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

Abstract: An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

Abstract: An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.

Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

Abstract: A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a third surface and a set of metal posts. The first die and the second die are stacked such that the third surface of the second die faces the second surface of the first die, and each metal post extends through a corresponding through-hole to a point beyond the first surface of the first die, electrically coupling the first die and the second die.

Abstract: A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads.

Abstract: A method for 3D device packaging utilizes through-substrate metal posts to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal posts. The first die and the second die are stacked such that each metal post extends from a surface of the second die toward a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal posts and the corresponding pads.

Abstract: A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface. A via extends through the substrate. The via is filled with conductive material and extends to at least the first major surface of the substrate. A thermal expansion inhibitor is over and in direct contact with the via proximate the first major surface. The thermal expansion inhibitor exerts a compressive stress on the conductive material closest to the thermal expansion inhibitor compared to the conductive material at a further distance from the thermal expansion inhibitor.

Abstract: A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

Abstract: A teleconferencing environment is provided in which both audio and visual cues are used to identify active participants and presenters. Embodiments provide an artificial environment, configurable by each participant in a teleconference, that directs the attention of a user to an identifier of an active participant or presenter. This direction is provided, in part, by stereo-enhanced audio that is associated with a position of a visual identifier of an active participant or presenter that has been placed on a window of a computer screen. The direction is also provided, in part, by promotion and demotion of attendees between attendee, active participant, and current presenter and automatic placement of an image related to an attendee on the screen in response to such promotion and demotion.