Abstract: A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process.

Abstract: A method of patterning an insulation layer is described. The method includes preparing a feature pattern in an insulation layer using at least one hard mask layer formed on the insulation layer, where the insulation layer contains a low-k material having a dielectric constant less than the dielectric constant of SiO2. The method further includes removing the at least one hard mask layer to expose a flat field surface of the insulation layer and, following the removing, forming a passivation layer on the flat field surface to protect the insulation layer using gas cluster ion beam (GCIB) irradiation of the insulation layer, wherein the GCIB irradiation is configured to grow or deposit the passivation layer on the flat field surface.

Abstract: A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process.

Abstract: A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV). The method includes providing a bonding wafer coupled to a handling wafer, and performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and selectively removing the planarized protective mask by an etching process. In one embodiment, the removing includes performing a first wet etching process that selectively removes a portion of the planarized trimmed bonding wafer relative to the planarized protective mask, and performing a second wet etching process that selectively removes the planarized protective mask.

Abstract: A process is provided for substrate ashing following the etching of features in a low dielectric constant (low-k) layer. The low-k layer can include ultra-low-k material, or a porous low-k material. The process may be configured to remove etch byproducts while preserving feature critical dimension. The ashing process comprises the use of a nitrogen and hydrogen containing chemistry with a passivation chemistry that includes oxygen, such as O2, CO, or CO2, or any combination thereof.

Abstract: The present invention comprises an aluminum base material 2 constituting the plasma processing chamber of the plasma processing apparatus, a bonding layer 3 deposited on the base material consisting of a transition metal or transition metal alloy that modifies the difference in thermal expansion coefficient of the base material and the material constituting a plasma contact surface, and the plasma contact surface 1 formed of a material selected from a group consisting of La2O3, LaAlO3, MgLaAl11O19, and a mixture of La2O3 and Al2O3 being a metal oxide including at least La and O deposited on the bonding layer 3 via a thermal spray process.

Abstract: The present invention comprises an aluminum base material 2 constituting the plasma processing chamber of the plasma proocessing apparatus, a bonding layer 3 deposited on the base material consisting of a transition metal or transition metal alloy that modifies the difference in thermal expansion coefficient of the base material and the material constituting a plasma contact surface, and the plasma contact surface 1 formed of a material selected from a group consisting of La2O3, LaAlO3, MgLaAl11O19, and a mixture of La2O3 and Al2O3 being a metal oxide including at least La and O deposited on the bonding layer 3 via a thermal spray process.