Abstract: A method and system for requesting an interrupt from a host system to service an adapter connected to the host system and a data interface. Data packets, including one or more data cells, are transferred between the data interface and the host system. The host system includes a host memory that includes a plurality of memory slots to store data packets transferred between the data interface and the host system. It is determined when a transfer of data has resulted in an occurrence of an interrupt event. An interrupt event occurs when the transfer of data includes a transfer of a data cell between the data interface and the host system and the data cell is defined to be an end of a data packet. In response to the occurrence of an interrupt event, it is determined whether to generate an interrupt request to the host system.

Abstract: A mechanism for mitigating the rate at which status reports associated with raw cell data transfers occur during receive operations in a network node is presented. The network node has an adapter for coupling a network and a host system, the host system including a host memory. The adapter operates to reassemble cell data received from the network and store the reassembled cell data in the host memory. A raw report holdoff counter is programmed to count a number corresponding to a preselected rx raw report holdoff value. If a raw cell data transfer request to be processed is detected, rx raw report information necessary to creating an rx raw cell status report is copied to a temporary storage area. When the data is transferred to the host system, the raw report holdoff counter is modified by one. When the modified counter has expired, the rx raw report information is written to a report queue in host memory.

Abstract: A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A holdoff timer is programmed to time a holdoff interval representing the time period to elapse before the generation of an interrupt request to the host system can occur. When a data transfer request associated with the transfer of data from or to the host system is serviced and results in the occurrence of an interrupt event, the holdoff event counter is modified by one. If either the holdoff event counter or the holdoff timer has expired and the interrupt is enabled, an interrupt request to the host system is generated. In response to such interrupt request generation, the interrupt is processed and both the holdoff event counter and the holdoff timer retriggered.

Abstract: A mechanism for avoiding an initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller to move data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

Abstract: A mechanism by which interrupt frequency mitigation is combined with transmit raw cell status report frequency mitigation is presented. A tx raw cell status report is allowed to occur for only every N raw cell tx slots consumed. When the rate of interrupt requests is mitigated in accordance with holdoff parameters including a holdoff event count corresponding to X interrupt events and a holdoff time interval, and the raw cell status report counts as an interrupt event, an interrupt request is generated for an enabled interrupt if N*X events has occurred or the holdoff time interval has elapsed.

Abstract: A mechanism for avoiding the initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller for moving data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

Abstract: A status report frequency mitigation mechanism for mitigating the frequency of status report generation for raw cells during transmit operations in a network node is presented. The status report frequency mitigation mechanism operates to adjust the frequency with which status reports for raw cells are generated by manipulating the End-of-Packet (EOP) bit in transmit slot descriptors associated with transmit slots containing raw cell data.

Abstract: Method and apparatus for scheduling operations of a network adapter in such a way as to minimize latency in processing received data packets, while still guaranteeing time for processing necessary background tasks. The method includes executing a polling loop in which repeated tests are made for the presence of receive data to process, but only a limited amount of receive data processing is performed before checking for background processing that needs to be performed. The polling loop ensures that immediate attention is given to processing of receive data, without the inherent latency of interrupt processing, but still gives periodic opportunities for background processing. Background processing is performed for a guaranteed minimum processing time before permitting a return to receive processing. Background processing may be performed without a guaranteed minimum processing time, but only when there is currently no receive processing to do.