Abstract: The invention broadly encompasses a signal processor of a High Capacity Waveform (HCW) that includes a method and system for generating the HCW, the method comprising the steps of receiving an encrypted source data packet and modulating a received encrypted source data signal representing the packet, wherein the modulating step further comprises the steps of encoding with high level data link control, scrambling the modulated signal, wherein the scrambling comprises applying digital logic, and encoding the scrambled signal, wherein the encoding comprises using a variable rate low density parity check (LDPC) code for forward error correction (FEC).