Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: Physical vapor deposition processes provide optical materials with controlled and uniform refractive index that meet the requirements for active and passive planar optical devices. All processes use radio frequency (RF) sputtering with a wide area target, larger in area than the substrate on which material is deposited, and uniform plasma conditions which provide uniform target erosion. In addition, a second RF frequency can be applied to the sputtering target and RF power can be applied to the substrate producing substrate bias. Multiple approaches for controlling refractive index are provided. The present RF sputtering methods for material deposition and refractive index control are combined with processes commonly used in semiconductor fabrication to produce planar optical devices such surface ridge devices, buried ridge devices and buried trench devices. A method for forming composite wide area targets from multiple tiles is also provided.

Abstract: Physical vapor deposition processes provide optical materials with controlled and uniform refractive index that meet the requirements for active and passive planar optical devices. All processes use radio frequency (RF) sputtering with a wide area target, larger in area than the substrate on which material is deposited, and uniform plasma conditions which provide uniform target erosion. In addition, a second RF frequency can be applied to the sputtering target and RF power can be applied to the substrate producing substrate bias. Multiple approaches for controlling refractive index are provided. The present RF sputtering methods for material deposition and refractive index control are combined with processes commonly used in semiconductor fabrication to produce planar optical devices such surface ridge devices, buried ridge devices and buried trench devices. A method for forming composite wide area targets from multiple tiles is also provided.

Abstract: Physical vapor deposition processes provide optical materials with controlled and uniform refractive index that meet the requirements for active and passive planar optical devices. All processes use radio frequency (RF) sputtering with a wide area target, larger in area than the substrate on which material is deposited, and uniform plasma conditions which provide uniform target erosion. In addition, a second RF frequency can be applied to the sputtering target and RF power can be applied to the substrate producing substrate bias. Multiple approaches for controlling refractive index are provided. The present RF sputtering methods for material deposition and refractive index control are combined with processes commonly used in semiconductor fabrication to produce planar optical devices such surface ridge devices, buried ridge devices and buried trench devices. A method for forming composite wide area targets from multiple tiles is also provided.

Abstract: Physical vapor deposition processes provide optical materials with controlled and uniform refractive index that meet the requirements for active and passive planar optical devices. All processes use radio frequency (RF) sputtering with a wide area target, larger in area than the substrate on which material is deposited, and uniform plasma conditions which provide uniform target erosion. In addition, a second RF frequency can be applied to the sputtering target and RF power can be applied to the substrate producing substrate bias. Multiple approaches for controlling refractive index are provided. The present RF sputtering methods for material deposition and refractive index control are combined with processes commonly used in semiconductor fabrication to produce planar optical devices such surface ridge devices, buried ridge devices and buried trench devices. A method for forming composite wide area targets from multiple tiles is also provided.