Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: A method for making an integrated circuit includes the step of fabricating a nonconductive layer (22, 23, 27, 29) having therein a lead trench (41) and having therethrough a via channel (36) which communicates with the lead trench. A liner (46) is applied on the nonconductive layer, a metal layer (47) is applied on the liner, and then heat and pressure are applied to extrude the metal layer into the lead trench and the via channel. A planarizing process is thereafter carried out to remove portions of the metal layer and the liner so as to create a planar surface (51) that includes coplanar surface portions on the nonconductive layer and on a portion of the metal layer remaining in the lead trench. The nonconductive layer may be fabricated by forming two dielectric layers which have therebetween an etch stop layer with openings, and then simultaneously etching both of the dielectric layers.

Abstract: A processing method for forming very shallow junctions 25 utilizing the differential diffusion coefficients of impurity dopants 38 in germanium as compared to silicon to confine the dopants 38 to very shallow regions made of substantially pure germanium 34. This processing method takes advantage of known and reliable process steps to create thin layers of Ge 34 with well-controlled thicknesses by conventional methods. The processing method includes the steps of forming a film layer of germanium of a desired thickness on the substrate 28; introducing a dopant material to the germanium film layer 34; and diffusing the dopant material in the germanium film layer 34.

Abstract: An isolation structure for bipolar and CMOS circuits formed during the same processing steps to optimize the integration of bipolar and CMOS circuits. A deep trench (46) is formed in a semiconductor circuit for providing deep isolation for bipolar circuits. A shallow recess (56) is then formed, which also forms a stepped sidewall structure of the deep trench. The recess (56) and the trench (46) are covered by an insulating oxide (60), and thereafter filled with an undoped polysilicon (62) to form the different isolating structures for the different types of circuits.

Abstract: Via patterns (16, 18) are applied to a first interlevel oxide layer (58) down to a metal layer (52) to define a plurality of orifices. These orifices (61, 63) are filled with tungsten by selective chemical vapor deposition. A first level conductor pattern (10, 12, 14) is then used to etch away the first insulator layer (58) and portions of plugs (62, 64) that are outside the first level conductor pattern. This first level conductor pattern is also used for a subsequent first level metal etch. The entire structure is then covered with a self-planarizing oxide layer (82), which is subsequently etched back to expose the top surfaces (66, 68) of tungsten plugs (62, 64).

Abstract: Disclosed is a process for forming a bipolar transistor at the face (22) of a semiconductor layer. A refractory metal layer (34) is deposited on the face (22) to cover a base area (38) thereof. A dopant (40) is implanted through the metal layer (34) within the base area (38) to penetrate the face (22). The metal layer (34) is then removed from the face within an emitter area (48) contained within the base area (38). A dopant is then diffused into the face within the emitter area (48). Finally, the dopants are annealed to form a shallow base region (66) that spaces an emitter region (64) from a collector region (12, 14). The process of the invention can form a high-concentration emitter/base junction only 400 Angstroms from the surface of the semiconductor layer.

Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer. The method includes forming an isolation trench, viewed in plan, having corners that are angled at about 45 degrees.

Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.

Abstract: An isolation structure for bipolar and CMOS circuits formed during the same processing steps to optimize the integration of bipolar and CMOS circuits. A deep trench (46) is formed in a semiconductor circuit for providing deep isolation for bipolar circuits. A shallow recess (56) is then formed simultaneous with a stepped sidewall structure of the deep trench. The recess (56) and the trench (46) are covered by an insulating oxide (60). and thereafter filled with an undoped polysilicon (62) to form the different isolating structures for the different types of circuits.

Abstract: A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.

Abstract: Via patterns (16, 18) are applied to a first interlevel oxide layer (58) down to a metal layer (52) to define a plurality of orifices. These orifices (61, 63) are filled with tungsten by selective chemical vapor deposition. A first level conductor pattern (10, 12, 14) is then used to etch away the first insulator layer (58) and portions of plugs (62, 64) that are outside the first level conductor pattern. This first level conductor pattern is also used for a subsequent first level metal etch. The entire structure is then covered with a self-planarizing oxide layer (82), which is subsequently etched back to expose the top surfaces (66, 68) of tungsten plugs (62, 64).

Abstract: Metal contacts and interconnections for integrated circuits utilize copper as the primary conductor, with the copper being totally encased in refractory metal layers on both top and bottom surfaces and also sidewalls. The contact hole in silicon oxide may be filled with a plug of refractory metal before the copper is deposited, or the first refractory metal layer may be conformally deposited to coat the sidewalls of the hole.

Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer.

Abstract: A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.

Abstract: Metal contacts and interconnections for integrated circuits utilize copper as the primary conductor, with the copper being totally encased in refractory metal layers on both top and bottom surfaces and also sidewalls. The contact hole in silicon oxide may be filled with a plug of refractory metal before the copper is deposited, or the first refractory metal layer may be conformally deposited to coat the sidewalls of the hole.

Abstract: A method of plating an interconnect or contact metal of higher conductivity than aluminum onto a metal layer in VLSI devices includes depositing a coating of insulator over the metal layer, patterning and etching the insulator coating into a mask of the reverse image of a desired lead pattern and then depositing the interconnect metal onto the exposed metal layer. Following depositing the insulator mask and underlaying metal is selectively removed.