Abstract: A multiplexing system couples a pair of input ports to a either a dual ported disk drive or a single ported disk drive. The system includes a multiplexer having the pair of first ports and a pair of second ports. The multiplexer is configurable to couple each one of the pair of first ports to a corresponding one of the pair of second ports when the pair of second ports are coupled to the dual ported disk drive and to couple both pair of first ports to a single one of the second ports when a single ported disk drive is coupled to said single one of the second ports.

Abstract: A data storage system includes a first chassis that has a pair of storage processors, a pair of SAS expanders having a bidirectional front end port and a plurality of bidirectional backend ports, and an expansion port, a pair of SAS controller each one being coupled between a corresponding one of the pair of processors and a corresponding one of the pair of the expanders, and a first plurality of multiplexers. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of a corresponding one of the pair of SAS expanders, a second one of the pair of bidirectional front end ports is connected to a corresponding backend port of a corresponding one of the pair of SAS expanders. The first chassis also has a plurality of disk drives, each one being coupled to at least one backend port of a corresponding one of the first plurality of multiplexers.

Abstract: Data storage equipment includes a first storage processor comprising a processing circuit and a collection of packaged integrated circuit devices which has a first set of ports and a second set of ports; a second storage processor; and an interconnect coupled between the first and second storage processors. The processing circuit of the first storage processor is adapted to execute as follows. The collection of packaged integrated circuit devices of the first storage processor is configured to provide (i) communications to a set of storage devices through the first set of ports of the collection of packaged integrated circuit devices and (ii) other communications to the second storage processor through the second set of ports of the collection of packaged integrated circuit devices. Communications is passed between the first storage processor and the set of storage devices through the first set of ports of the collection of packaged integrated circuit devices.

Abstract: Single and dual ported devices are interfaced to a system via a 2:2 multiplexing device. The multiplexing device is coupled to two system ports and two device ports. The multiplexing device includes an active multiplexer coupled to the two system ports and a multiplexed port. The multiplexing device also includes bypass circuitry coupled to the two system ports and two bypass ports. In operation, when the multiplexing device is coupled via one of the device ports to a single ported device such as a single ported disk drive, the active multiplexer is activated and the bypass circuitry is deactivated and the multiplexed port is coupled to the device port. When the multiplexing device is coupled via both device ports to a dual ported device, the active multiplexer is deactivated and the bypass circuitry is activated and the bypass ports are coupled to the two device ports.

Abstract: A system and method of testing processor boards in which a test path is created by setting switches in distribution hubs and the devices under test. Test signals are sent through the test path and errors in the signals are used to identify faulty boards. The distribution hubs of an embodiment can detect, report and eliminate errors in the test signals. A command path from a host to the distribution hubs and devices under test is provided through a multi-terminal connector. The command path is preferably separate from the test path. A test signal generator may be included. The system may be particularly adapted for fiber channel testing.